Timing Of Setting Of Watchdog Timer Overflow Flag (Wovf); Figure 12.3 Timing Of Wovf Setting - Hitachi H8S/2215 Series Hardware Manual

12.3.2

Timing of Setting of Watchdog Timer Overflow Flag (WOVF)

With WDT0, the WOVF bit in RSTCSR is set to 1 if TCNT overflows in watchdog timer mode.
If TCNT overflows while the RSTE bit in RSTCSR is set to 1, an internal reset signal is generated
for the entire chip. This timing is illustrated in figure 12.3.
ø
TCNT
Overflow signal
(internal signal)
WOVF
Internal reset
signal
Rev. 3.0, 10/02, page 352 of 686
H'FF

Figure 12.3 Timing of WOVF Setting

H'00
518 states (WDT0)