External Connection Diagram Of External Bus Interface (Example Of Connection With V850E/Me2) - NEC V850E/MA1 Application Note

CHAPTER 4 CONFIGURATION EXAMPLES OF FPGA INTEGRATION

4.5.3 External connection diagram of external bus interface (example of connection with V850E/ME2)

System reset
FPGA
(PCI host bridge)
VBRESETZ RA2 to RA14
RA24, RA25
RD0 to RD31
BENZ0 to BENZ3
V850E/ME2
RESET
xxBE/xxDQM
Remarks 1. This is an example using two SDRAMs of 4 M words × 16 bits × 4 banks (row address: 13 bits,
column address: 9 bits).
2. xx: LL, LU, UL, UU
WRZ
SDCKE
SDCS
SDRASZ
SDCASZ
SDCLK
RDZ
WAITZ
INT0
HLDRQZ
HLDAKZ
HLDAK
HLDRQ
INTPxxx
WAIT
RD
A0 to A22
A24, A25
D0 to D31
WR/WE
SDCKE
CSx
SDRAS
SDCAS
BUSCLK
Application Note U17121EJ1V1AN
SDRAM1
SDRAM2
A0 to A12
BA0, BA1
DQ0 to DQ31
DQM0, DQM1 DQM2, DQM3
/WE
CKE
/CS
/RAS
/CAS
CLK
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