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CONTENTS
SVD3 Interrupt Enable Register ............................................................................................ 11-8
12 16-bit Timers (T16) .....................................................................................................12-1
12.1 Overview ...................................................................................................................... 12-1
12.2 Input Pin ....................................................................................................................... 12-1
12.3 Clock Settings .............................................................................................................. 12-2
12.3.1 T16 Operating Clock ........................................................................................... 12-2
12.3.2 Clock Supply in SLEEP Mode ............................................................................. 12-2
12.3.3 Clock Supply During Debugging ......................................................................... 12-2
12.3.4 Event Counter Clock ........................................................................................... 12-2
12.4 Operations ................................................................................................................... 12-2
12.4.1 Initialization .......................................................................................................... 12-2
12.4.2 Counter Underflow .............................................................................................. 12-3
12.4.3 Operations in Repeat Mode ................................................................................ 12-3
12.4.4 Operations in One-shot Mode ............................................................................. 12-3
12.4.5 Counter Value Read ............................................................................................ 12-4
12.5 Interrupt ........................................................................................................................ 12-4
12.6 Control Registers ......................................................................................................... 12-4
T16 Ch.n Clock Control Register .......................................................................................... 12-4
T16 Ch.n Mode Register ...................................................................................................... 12-5
T16 Ch.n Control Register .................................................................................................... 12-5
T16 Ch.n Reload Data Register ............................................................................................ 12-6
T16 Ch.n Counter Data Register .......................................................................................... 12-6
T16 Ch.n Interrupt Flag Register .......................................................................................... 12-6
T16 Ch.n Interrupt Enable Register ...................................................................................... 12-7
13 UART (UART3) ............................................................................................................13-1
13.1 Overview ...................................................................................................................... 13-1
13.2 Input/Output Pins and External Connections .............................................................. 13-2
13.2.1 List of Input/Output Pins ..................................................................................... 13-2
13.2.2 External Connections .......................................................................................... 13-2
13.2.3 Input Pin Pull-Up Function .................................................................................. 13-2
13.2.4 Output Pin Open-Drain Output Function ........................................................... 13-2
13.2.5 Input/Output Signal Inverting Function ............................................................... 13-2
13.3 Clock Settings .............................................................................................................. 13-2
13.3.1 UART3 Operating Clock ...................................................................................... 13-2
13.3.2 Clock Supply in SLEEP Mode ............................................................................. 13-3
13.3.3 Clock Supply During Debugging ......................................................................... 13-3
13.3.4 Baud Rate Generator .......................................................................................... 13-3
13.4 Data Format ................................................................................................................. 13-3
13.5 Operations ................................................................................................................... 13-4
13.5.1 Initialization .......................................................................................................... 13-4
13.5.2 Data Transmission ............................................................................................... 13-5
13.5.3 Data Reception .................................................................................................... 13-6
13.5.4 IrDA Interface ...................................................................................................... 13-7
13.5.5 Carrier Modulation ............................................................................................... 13-8
13.6 Receive Errors .............................................................................................................. 13-9
13.6.1 Framing Error ....................................................................................................... 13-9
13.6.2 Parity Error ........................................................................................................... 13-9
13.6.3 Overrun Error ....................................................................................................... 13-9
13.7 Interrupts ..................................................................................................................... 13-10
13.8 DMA Transfer Requests .............................................................................................. 13-10
13.9 Control Registers ........................................................................................................ 13-11
UART3 Ch.n Clock Control Register ................................................................................... 13-11
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Seiko Epson Corporation
S1C31D50/D51 TECHNICAL MANUAL
(Rev. 2.00)
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