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2
16 I
C (I2C)
I2C Ch.n Transmit Buffer Empty DMA Request Enable Register
Register name
Bit
I2C_nTBEDMAEN
15–0 TBEDMAEN[15:0]
Bits 15–0 TBEDMAEN[15:0]
These bits enable the I2C to issue a DMA transfer request to the corresponding DMA controller chan-
nel (Ch.0–Ch.15) when a transmit buffer empty state has occurred.
1 (R/W): Enable DMA transfer request
0 (R/W): Disable DMA transfer request
Each bit corresponds to a DMA controller channel. The high-order bits for the unimplemented chan-
nels are ineffective.
I2C Ch.n Receive Buffer Full DMA Request Enable Register
Register name
Bit
I2C_nRBFDMAEN
15–0 RBFDMAEN[15:0]
Bits 15–0 RBFDMAEN[15:0]
These bits enable the I2C to issue a DMA transfer request to the corresponding DMA controller chan-
nel (Ch.0–Ch.15) when a receive buffer full state has occurred.
1 (R/W): Enable DMA transfer request
0 (R/W): Disable DMA transfer request
Each bit corresponds to a DMA controller channel. The high-order bits for the unimplemented chan-
nels are ineffective.
16-24
Bit name
Initial
0x0000
Bit name
Initial
0x0000
Seiko Epson Corporation
Reset
R/W
H0
R/W
–
Reset
R/W
H0
R/W
–
S1C31D50/D51 TECHNICAL MANUAL
Remarks
Remarks
(Rev. 2.00)
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