Table Base Address Registers - Yamaha V9938 Programmer's Manual

Line:
R#9 LN
count is 192
S1 Selects simultaneous mode
S0 Selects simultaneous mode
Interlace:
IL
Even/Odd screens:
EO
interchangeably by even/odd field; if set to 0, displays same graphic
screen by even/odd field
*NT (RGB output only) If set to 1, PAL mode (313 lines, 50Hz); if set to 0,
NTSC mode (262 lines, 60Hz)
Dot clock:
DC
output mode

2.1.2. Table Base address registers

When displaying information on the screen, VDP uses color, pattern, sprite and other
information from video RAM. It is important to set proper starting addresses of such VRAM
locations by writing to specified table base address registers.
Note: you should ensure that unused bits are set to 0. Further in the book bit set to
"0" will mean that this bit has to be set to 0, "1" will mean that this bit has to be set to 1,
and "*" will mean that value of the bit does not matter.
MSB
R#2
R#3
R#10
R#4
R#5
R#11
R#6
© 1985 ASCII CORP. / NIPPON GAKKI CO.
if set to 1, vertical dot count is set to 212. If set to 0, vertical dot
if set to 1, interlace; if set to 0, non-interlace mode
When set to 1, displays two graphic screens
If set to 1, *DLCLK is in input mode; if set to 0, *DLCKL is in
7 6 5
0 A16 A15
A13 A12 A11
0 0 0
0 0 A16
A14 A13 A12
0 0 0
0 0 A16
4 3 2
A14 A13 A12
A10 A9 A8
0 0 A16
A15 A14 A13
A11 A10 A9
0 0 0
A15 A14 A13
Page 18 of 108
1 0 LSB
A11 A10 Pattern layout
table
A7 A6 Color table low
A15 A14 Color table high
A12 A11 Pattern
generator table
A8 A7 Sprite attribute
table low
A16 A15 Sprite attribute
table high
A12 A11 Sprite pattern
generator table
© 2010-2015 Eugeny Brychkov