Yamaha V9938 Programmer's Manual
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Yamaha V9938 Programmer's Manual

Yamaha V9938 Programmer's Manual

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V9938 MSX-VIDEO
Technical Data Book
Programmer's Guide
ASCII CORPORATION / NIPPON GAKKI CO., LTD.
NIPPON GAKKI CO., LTD.
© 1985 ASCII CORP. / NIPPON GAKKI CO.
© 2010-2015 Eugeny Brychkov
Page 1 of 108

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Summary of Contents for Yamaha V9938

  • Page 1 V9938 MSX-VIDEO Technical Data Book Programmer’s Guide ASCII CORPORATION / NIPPON GAKKI CO., LTD. NIPPON GAKKI CO., LTD. © 1985 ASCII CORP. / NIPPON GAKKI CO. © 2010-2015 Eugeny Brychkov Page 1 of 108...
  • Page 2 This page is intentionally left blank © 1985 ASCII CORP. / NIPPON GAKKI CO. © 2010-2015 Eugeny Brychkov Page 2 of 108...
  • Page 3 IT market. V9938 is one of the most popular video-processors in the family of Texas Instruments original chips, improved by a group of companies from Japan and US. Its follower, V9958, was a VDP chip for limited release of MSX2+ and MSX Turbo-R machines, and the last VDP in the family, V9990, can only be found in add-on cartridges.
  • Page 4 This page is intentionally left blank © 1985 ASCII CORP. / NIPPON GAKKI CO. © 2010-2015 Eugeny Brychkov Page 4 of 108...

  • Page 5: Screen Modes 2

    NAPLPS terminals using the V9938 have already been developed. We hope that the V9938 will be a standard video processing device on a worldwide basis. This manual was written to explain how to set parameters of the v9938 and is a reference for developing applications and system software for it.
  • Page 6 This page is intentionally left blank © 1985 ASCII CORP. / NIPPON GAKKI CO. © 2010-2015 Eugeny Brychkov Page 6 of 108...

  • Page 7: Table Of Contents

    CONTENTS DEFINITIONS ....................9 1. BASIC INPUT AND OUTPUT..............1 3 1.1. Accessing the Control Registers ..............13 1.1.1. Direct access to VDP registers............13 1.1.2. Indirect access to registers through R#17 (Control Register Pointer) ..13 1.2. Accessing the Palette Registers...............14 1.3. Accessing the Status Registers..............14 1.4.
  • Page 8 4.4.7. LMMM (Logical move VRAM to VRAM)..........81 4.4.8. LMMV (logical move VDP to VRAM) ..........83 4.4.9. LINE .....................85 4.4.10. SRCH ..................87 4.4.11. PSET ...................90 4.4.12. POINT..................92 4.5. Speeding up the processing of commands ..........93 4.6. States of the registers after command execution ........94 5.

  • Page 9: Definitions

    DEFINITIONS Attribute The property of an object, which controls how object looks like on the screen. Attribute can be a color, position of an object, or control which pixel should have specific color Background object property Is an which is perceived to be in the background to another property or object.
  • Page 10 Layout A map of patterns or sprites which identify where to display specific object or which object should be displayed in specific position. In case of patterns (font), Pattern generator Table identifies the appearance of font, but in order to display these patterns in specific position, programmer should put its number into Pattern Layout Table in respective location Object Font patterns or a sprite.
  • Page 11 Picture displaying occurs continuously when VDP is enabled. V9938 may have 16K to 128K VRAM, and depending on the memory organization and size may not be able to function properly in specific modes. See description of register R#8’s bit VR for more information...
  • Page 12 This page is intentionally left blank © 1985 ASCII CORP. / NIPPON GAKKI CO. © 2010-2015 Eugeny Brychkov Page 12 of 108...

  • Page 13: Basic Input And Output

    1. BASIC INPUT AND OUTPUT 1.1. Accessing the Control Registers V9938 has 4 ports: port #0 – port #3; port number is selected by VDP address lines A0 and A1. Table below also shows port address allocation for MSX compatible machine.

  • Page 14: Accessing The Palette Registers

    Note: data in register R#17 can not be changed by indirect addressing. Register #17 Register # 0: Auto-increment is enabled 1: Auto-increment is disabled Port #3 first byte Data Port #3 second byte Data … Port #3 n byte Data 1.2.
  • Page 15 1.4. Accessing the Video RAM (VRAM) A video RAM of 128K bytes plus an expansion RAM of 64K bytes can be attached to the VDP. Memory map is shown below. Address 1FFFFh ↑ ↑ ↑ ↑ 10000h 0FFFFh ↑ ↑ ↑...
  • Page 16 Step 2: Setting the address counter A16 to A14 VDP can logically address 128K bytes in the address range of 00000h-1FFFFh through 16 address bits A16…A0. At this step we set up bits A16…A14 writing them into register R#14 (VRAM access base address register). Register #14 Base reg Step 3: Setting the address counter A7 to A0...

  • Page 17: Register Functions

    2. REGISTER FUNCTIONS 2.1. Control registers 2.1.1. Mode registers Mode R#0 Mode R#1 Mode R#8 Mode R#9 * Indicates negative logic Digitize mode: sets the color bus to the input or output mode Enables interrupts from Light pen Enables interrupt from horizontal retrace Screen mode flag (see Screen Modes chapter) Screen mode flag (see Screen Modes chapter) Screen mode flag (see Screen Modes chapter)

  • Page 18: Table Base Address Registers

    Line: if set to 1, vertical dot count is set to 212. If set to 0, vertical dot count is 192 Selects simultaneous mode Selects simultaneous mode Interlace: if set to 1, interlace; if set to 0, non-interlace mode Even/Odd screens: When set to 1, displays two graphic screens interchangeably by even/odd field;...

  • Page 19: Color Registers

    2.1.3. Color registers Color registers are used to control MSX-VIDEO text and background screen colors, blinking and other functions. Text and screen margin color Text color in TEXT1 and Screen margin / TEXT2 modes backdrop color R#12 Text and background Color part 1 Color part 0 blink color...

  • Page 20: Display Registers

    2.1.4. Display registers The display registers are used to control display position on the screen. R#18 Display adjust register Register #18 controls horizontal and vertical alignment on the screen. Please refer to the table below. Value … … Left … …...

  • Page 21: Access Registers

    R#19 Interrupt line register VDP generates interrupt when it starts to display respective scan line if bit 4 “IE1” of register R#0 is set to 1. Write a value to this register R#19, and when VDP will start displaying the specified line, it will set bit 0 “FH” of status register S#1 to 1. 2.1.5.

  • Page 22: Command Registers

    2.1.6. Command registers The following command registers are used when executing a command on the MSX- VIDEO. Details on the use of these command registers will be presented in later chapter. R#32 Source X low register R#33 Source X high register R#34 Source Y low...

  • Page 23: Status Registers #0 To #9

    2.2. Status registers #0 to #9 The following status registers are read-only registers for VDP status reporting. Let’s consider each register. Status register 0 Vertical scan interrupt flag. When S#0 is read, this flag is reset Flag for 5 sprite. Five (or nine in G3…G7 modes) sprites are aligned on the same horizontal line Collision flag.
  • Page 24 Column register Column register high Row register Row register high The above registers S#3…S#6 contain coordinate information about collision location of the sprites, or location of light pen, or relative movement of the mouse. Color register This color register is used when executing commands “POINT” and “VRAM to CPU” and contains VRAM data.

  • Page 25: Screen Modes

    3. SCREEN MODES 3.1. TEXT1 mode Characteristics Pattern size (w*h) 6 dots * 8 dots Patterns 256 types Screen size (w*h) 40 * 24 patterns Pattern colors Two colors out of 512 (per screen) VRAM area per screen 4K bytes Controls Pattern font VRAM pattern generator table...
  • Page 26 3.1.2. Pattern Generator Table The pattern generator table is a location in VRAM that stores patterns (font). Each pattern has number from PN0 to PN255. The font displayed on the screen for each pattern is constructed from 8 bytes, with 6 high-order bits displayed and 2 low-order bits not displayed.
  • Page 27 3.1.3. Pattern Layout Table settings The pattern layout table is a map of the screen (per screen image). Every location of the screen contains code of the pattern displayed at respective location. This table has 40*24 (960) locations where defined patterns can be displayed. Pattern layout table base address is stored in register R#2, and corresponds to the cell (0, 0) with address 0 in the picture below.
  • Page 28 3.1.5. Example of VRAM allocation for TEXT1 mode 00000h Pattern layout table 0 A16 A15 A14 A13 A12 A11 A10 003BFh 00800h Pattern generator table 0 A16 A15 A14 A13 A12 A11 00FFFh 01000h Pattern layout table 1 A16 A15 A14 A13 A12 A11 A10 013BFh 01800h Pattern generator...

  • Page 29: Text2 Mode

    3.2. TEXT2 mode Characteristics Pattern size (w*h) 6 dots * 8 dots Patterns 256 types Screen size (w*h) 80 * 24 patterns if LN bit of R#9 set to 0 80 * 26.5 patterns if LN bit of R#9 set to 1 Pattern colors Two colors out of 512 (per screen), four if using blinking VRAM area per screen...
  • Page 30 3.2.2. Pattern Generator Table Organization of pattern generator table is the same as in TEXT1 mode. Register R#4 defines base address of the table. 3.2.3. Pattern layout table settings The pattern layout table is a map of the screen (per screen image). Every location of the screen contains code of the pattern displayed at respective location.
  • Page 31 Screen mapping of color table is provided below. (0, 0) (1, 0) (2, 0) (3, 0) (4, 0) (5, 0) (6, 0) (7, 0) (8, 0) (9, 0) (10, 0) (11, 0) (12, 0) (13, 0) (14, 0) (15, 0) …...
  • Page 32 The NTSC timing data is provided in the table below. Delay data (binary) Time (ms) Delay data (binary) Time (ms) 0 0 0 0 1 0 0 0 1335.1 0 0 0 1 166.9 1 0 0 1 1509.9 0 0 1 0 333.8 1 0 1 0 1668.8...
  • Page 33 3.2.7. Example of VRAM allocation for TEXT2 mode 00000h Pattern layout table 0 A16 A15 A14 A13 A12 00870h 00A00h Color table 0 00B0Eh A13 A12 A11 A10 A9 01000h Pattern generator table 0 R#10 A16 A15 A14 01800h A16 A15 A14 A13 A12 A11 02000h Pattern layout table 1...

  • Page 34: Multicolor (Mc) Mode

    3.3. MULTICOLOR (MC) mode Characteristics Screen composition (w*h) 64 * 48 color blocks Color blocks Sixteen colors out of 512 colors Sprite mode Sprite mode 1 VRAM area per screen 4K bytes Controls Color block color code VRAM pattern generator table Color block location VRAM pattern name table Background color code...
  • Page 35 3.3.1. Pattern Generator Table Each pattern is made up of four color blocks. These patterns are of size of 8*8 for the screen display of 256*192 dots. ← 8 dots → For each block A, B, C, and D sixteen colors can be Block A Block B ↑...
  • Page 36 Columns ← X … … … … … … … … … … … … … … … … … … … … … … … … ↑ 3.3.3. Color register settings You can set color of the margin of the screen (backdrop color) specifying BD3…BD0 bits in register R#7.
  • Page 37 3.3.5. Example of VRAM allocation for MULTICOLOR mode 00000h Sprite generator table 0 00400h 00400h Pattern layout table 0 00700h 00700h Sprite attribute table 0 00780h 00800h Pattern generator table 0 01000h Maximum of 32 pages may be allocated in the same manner if VDP has 128K bytes attached to it.

  • Page 38: Graphic1 (G1) Mode

    3.4. GRAPHIC1 (G1) mode Characteristics Pattern size (w*h) 8 dots * 8 dots Patterns 256 types Screen size (w*h) 32 * 24 patterns (256 * 192 pixels) Pattern colors 16 colors out of 512 (per screen) Sprite mode Sprite mode 1 VRAM area per screen 4K bytes Controls...
  • Page 39 3.4.1. Pattern Generator Table The pattern generator table is a location in VRAM that stores patterns (font). Each pattern has number from PN0 to PN255. The font displayed on the screen for each pattern is constructed from 8 bytes, with all 8 bits of each byte displayed. Pattern generator table base is stored in the register R#4.
  • Page 40 table base address is stored in register R#2, and corresponds to the cell (0, 0) with address 0 in the picture below. Columns ← X … … … … … … … … … … … … … … … …...
  • Page 41 3.4.5. Sprite settings Set the start address of the sprite attribute table in registers R#5 and R#11; set start address of the sprite pattern generator table in register R#6. For details about sprites please refer to section “Sprite mode 1”. 3.4.6.

  • Page 42: Graphic2 (G2) And Graphic3 (G3) Modes

    3.5. GRAPHIC2 (G2) and GRAPHIC3 (G3) modes Characteristics Pattern size (w*h) 8 dots * 8 dots Patterns 768 types (256 per ⅓ of the screen) Screen size (w*h) 32 * 24 patterns (256 * 192 pixels) Pattern colors 16 colors out of 512 (per screen) Sprite mode* Sprite mode 1 (GRAPHIC 2) Sprite mode 2 (GRAPHIC 3)
  • Page 43 3.5.1. Screen map and pattern tables Unlike in other modes, in this mode screen is divided vertically into three logical parts. Every part has its own pattern generator and pattern color tables, but all of them share the same pattern layout table, one after another. Screen map is provided below. Columns ←...
  • Page 44 3.5.2. Pattern Tables The pattern generator table is a location in VRAM that stores patterns (font). Each pattern has number from PN0 to PN255, for every ⅓ of the screen. The font displayed on the screen for each pattern is constructed from 8 bytes, with all 8 bits of each byte displayed.
  • Page 45 ● ● ● ● ● ● 2040 1 1 1 1 0 0 0 0 2040 2041 1 1 1 1 0 0 0 0 2041 2042 1 1 1 1 0 0 0 0 2042 Pattern 2043 1 1 1 1 0 0 0 0 2043 number 2044 1 1 1 1 0 0 0 0 2044...
  • Page 46 3.5.6. Example of VRAM allocation for GRAPHIC2 and GRAPHIC3 modes 00000h Pattern generator table, upper 007FFh 00800h Pattern generator GRAPHIC2 mode GRAPHIC3 mode table, middle Sprite 01800h Sprite 01800h pattern pattern 00FFFh table table 01000h Pattern generator 01BFFh 01BFFh table, lower Sprite 01C00h Sprite color...

  • Page 47: Graphic4 (G4) Mode

    3.6. GRAPHIC4 (G4) mode Characteristics Bit-mapped Graphics mode Screen size (w*h) 256 * 192 pixels if LN bit of R#9 set to 0 256 * 212 pixels if LN bit of R#9 set to 1 Pattern colors 16 colors out of 512 (per screen) Sprite mode Sprite mode 2 VRAM area per screen...
  • Page 48 3.6.1. Pattern layout table settings The pattern layout table is a map of the screen (per screen image). Every byte location of the screen contains color codes for two dots. This is bitmap graphics mode, and there’s no pattern generator table. Columns ←...
  • Page 49 3.6.3. Sprite settings Set the start address of the sprite attribute table in registers R#5 and R#11; set start address of the sprite pattern generator table in register R#6. For details about sprites please refer to section “Sprite mode 2” Sprite attribute table low R#11...

  • Page 50: Graphic5 (G5) Mode

    3.7. GRAPHIC5 (G5) mode Characteristics Bit-mapped Graphics mode Screen size (w*h) 512 * 192 pixels if LN bit of R#9 set to 0 512 * 212 pixels if LN bit of R#9 set to 1 Pattern colors 4 colors out of 512 (per screen) Sprite mode Sprite mode 2 VRAM area per screen...
  • Page 51 3.7.1. Pattern layout table settings The pattern layout table is a map of the screen (per screen image). Every byte location of the screen contains color codes for four dots. This is bitmap graphics mode, and there’s no pattern generator table. Columns ←...
  • Page 52 3.7.2. Color register settings You can set color of the margin of the screen (backdrop color) specifying BD3…BD0 bits in register R#7. Note that bits TC3…TC0 of R#7 are ignored. 3.7.3. Sprite settings Set the start address of the sprite attribute table in registers R#5 and R#11; set start address of the sprite pattern generator table in register R#6.
  • Page 53 Actual sprite representation on the screen in G5 mode (8*8 size) Offset 7 6 5 4 3 2 1 0 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 0 X X X 0 0 1 1 1 1 X X X 0 0 1 1 1...
  • Page 54 3.7.5. Example of VRAM allocation for GRAPHIC5 mode 00000h Pattern name table Sprite 07000h 02000h pattern table 04000h Sprite color 07800h table 192 lines 06000h 212 lines Sprite 07A00h 06A00h attribute table 07000h 07A80h 08000h Maximum of 4 pages may be allocated in the same manner 1FFFFh if VDP has 128K bytes attached to it.

  • Page 55: Graphic6 (G6) Mode

    3.8. GRAPHIC6 (G6) mode Characteristics Bit-mapped Graphics mode Screen size (w*h) 512 * 192 pixels if LN bit of R#9 set to 0 512 * 212 pixels if LN bit of R#9 set to 1 Pattern colors 16 colors out of 512 (per screen) Sprite mode Sprite mode 2 VRAM area per screen...
  • Page 56 3.8.1. Pattern layout table settings The pattern layout table is a map of the screen (per screen image). Every byte location of the screen contains color codes for two dots. This is bitmap graphics mode, and there’s no pattern generator table. Columns ←...
  • Page 57 3.8.2. Color register settings You can set color of the margin of the screen (backdrop color) specifying BD3…BD0 bits in register R#7. Note that bits TC3…TC0 of R#7 are ignored. 3.8.3. Sprite settings Set the start address of the sprite attribute table in registers R#5 and R#11; set start address of the sprite pattern generator table in register R#6.
  • Page 58 3.8.4. Example of VRAM allocation for GRAPHIC4 mode 00000h Pattern name table Sprite 0F000h 04000h pattern table 08000h Sprite color 0F800h table 192 lines 0C000h 212 lines Sprite 0FA00h 0D400h attribute table 0F000h 0FA80h 10000h Maximum of 2 pages may be allocated in the same manner 1FFFFh if VDP has 128K bytes attached to it.

  • Page 59: Graphic7 (G7) Mode

    3.9. GRAPHIC7 (G7) mode Characteristics Bit-mapped Graphics mode Screen size (w*h) 256 * 192 pixels if LN bit of R#9 set to 0 256 * 212 pixels if LN bit of R#9 set to 1 Pattern colors 256 colors (per screen) Sprite mode Sprite mode 2 VRAM area per screen...
  • Page 60 3.9.1. Pattern layout table settings The pattern layout table is a map of the screen (per screen image). Every byte location of the screen contains color code for one single dot. This is bitmap graphics mode, and there’s no pattern generator table. Columns ←...
  • Page 61 3.9.2. Color register settings You can set color of the margin of the screen (backdrop color) specifying all the 8 bits in register R#7 (256 possible colors in total). Screen margin color Screen margin / backdrop color 3.9.3. Sprite settings Set the start address of the sprite attribute table in registers R#5 and R#11;...
  • Page 62 3.9.4. Example of VRAM allocation for GRAPHIC7 mode 00000h Pattern name table Sprite 0F000h 04000h pattern table 08000h Sprite color 0F800h table 192 lines 0C000h 212 lines Sprite 0FA00h 0D400h attribute table 0F000h 0FA80h 10000h Maximum of 2 pages may be allocated in the same manner 1FFFFh if VDP has 128K bytes attached to it.

  • Page 63: Commands

    4. COMMANDS 4.1. Types of commands Commands are used to perform specific complex operations on the video memory, and thus on the image displayed on the screen. See the list of available commands in the table below. Command Destination Source Unit Mnemonic name High-speed...

  • Page 64: Page Concept

    4.2. Page concept As we have already seen, programmer can have several options to place tables in the video memory by altering base address registers. In some modes there’re more options (like in Text 1 there’re 32 options and in GRAPHICS7 there’re only 2 options). This introduces a concept of the page defined by where VDP currently operates and where it takes information for picture display from.

  • Page 65: Logical Operations

    4.3. Logical operations When executing logical commands LINE, PSET and LOGICAL MOVE, it is possible to define logical operation to be done on the color of the pixels. The four bits identifying the logical operation should be written in lower four bits of R#46 (command register) together with the command code.

  • Page 66: Explanations Of Commands

    4.4. Explanation of the commands 4.4.1. HMMC (High speed move CPU to VRAM) HMMC command is used to transfer data from the CPU to video or expansion RAM into a specified rectangular area through VDP. When using this command, note the limitation on the X coordinate in various modes (255 or 511).
  • Page 67 R#44 G4, G6 (N=0..127) X=2N X=2N+1 G5 (N=0…127) X=4N X=4N+1 X=4N+2 X=4N+3 X=N (One dot) Step 3: Select destination memory and direction from base coordinate R#45 0: Right X transfer direction 1: Left 0: Down Y transfer direction 1: Up 0: VRAM Destination select...
  • Page 68 Flowchart of HMMC execution from CPU point of view HMMC Start Set up VDP registers Execute command Read status register #2 Yes (CE=0) End of command? No (CE=1) No (TR=0) Transmit ready? Yes (TR=1) Data transmit (R#44) HMMC End © 1985 ASCII CORP. / NIPPON GAKKI CO. ©...

  • Page 69: Ymmm (High Speed Move Vram To Vram, Y Only)

    4.4.2. YMMM (High speed move VRAM to VRAM, Y coordinate only) YMMM command is used to transfer data from the area specified by DX, SY, NY, DIX, DIY and the right (or left) edge of the screen, in the Y-direction determined by DY. Video or expansion RAM (DX, DY) →...
  • Page 70 Step 2: Select destination memory and direction from base coordinate R#45 0: Right X transfer direction 1: Left 0: Down Y transfer direction 1: Up 0: VRAM Destination select 1: ExpRAM Step 3: Execute the command R#46 YMMM cmd Step 4: Wait for command execution completion While command is being executed by VDP, CE bit of status register S#2 will be set to 1.

  • Page 71: Hmmm (High Speed Move Vram To Vram)

    4.4.3. HMMM (High speed move VRAM to VRAM) HMMM command is used to transfer data from one specific rectangular area in VRAM of expansion RAM to another area within VRAM of expansion RAM. Note the limitation on the X coordinate, which is dependent on the current graphics mode (255 or 511). Video or expansion RAM (SX, SY) →...
  • Page 72 Step 2: Select destination memory and direction from base coordinate R#45 MXD MSX 0: Right X transfer direction 1: Left 0: Down Y transfer direction 1: Up 0: VRAM Source location select 1: ExpRAM 0: VRAM Destination location select 1: ExpRAM Step 3: Execute the command R#46 HMMM cmd...

  • Page 73: Hmmv (High-Speed Move Vdp To Vram)

    4.4.4. HMMV (High speed move VDP to VRAM) HMMV command is used to paint in a specific rectangular area in the VRAM or expansion RAM. When using this command, note the limitation on the X coordinate in various modes (255 or 511). Video or expansion RAM (DX, DY) →...
  • Page 74 R#44 G4, G6 (N=0..127) X=2N X=2N+1 G5 (N=0…127) X=4N X=4N+1 X=4N+2 X=4N+3 X=N (One dot) Step 3: Select destination memory and direction from base coordinate R#45 0: Right X transfer direction 1: Left 0: Down Y transfer direction 1: Up 0: VRAM Destination select...

  • Page 75: Lmmc (Logical Move Cpu To Vram)

    4.4.5. LMMC (Logical move CPU to VRAM) LMMC command is used to transfer data from the CPU to video or expansion RAM into a specified rectangular area through VDP. The units used are dots. Video or expansion RAM (DX, DY) →...
  • Page 76 Step 3: Select destination memory and direction from base coordinate R#45 0: Right X transfer direction 1: Left 0: Down Y transfer direction 1: Up 0: VRAM Destination select 1: ExpRAM Step 4: Execute the LMMC command R#46 LMMC cmd Logical operation Step 5: Send data and wait for completion While command is being executed by VDP, CE bit of status register S#2 will be set to...
  • Page 77 Flowchart of LMMC execution from CPU point of view LMMC Start Set up VDP registers Execute command Read status register #2 Yes (CE=0) End of command? No (CE=1) No (TR=0) Transmit ready? Yes (TR=1) Data transmit (R#44) LMMC End © 1985 ASCII CORP. / NIPPON GAKKI CO. ©...

  • Page 78: Lmcm (Logical Move Vram To Cpu)

    4.4.6. LMCM (Logical move VRAM to CPU) LMCM command is used to transfer data from the video or expansion RAM in a specified rectangular area to the CPU through VDP. The units used are dots. Video or expansion RAM (SX, SY) →...
  • Page 79 Step 3: Clear the TR flag Read the value from status register S#7. This step is required in order to clear the TR flag. Please refer to flowchart in this section for the LMCM command. Step 4: Execute the LMCM command R#46 LMCM cmd Step 5: Read dot color code and check fir command end...
  • Page 80 Flowchart of LMCM execution from CPU point of view LMCM Start Set up VDP registers* Execute command Read status register #2 No (TR=0) Transmit ready? Yes (TR=1) Read status register S#7 Command end? No (CE=1) Yes (CE=0) LMMC End *TR must be cleared before command execution ©...

  • Page 81: Lmmm (Logical Move Vram To Vram)

    4.4.7. LMMM (Logical move VRAM to VRAM) LMMM command is used to transfer data from one specific rectangular area in VRAM of expansion RAM to another area within VRAM of expansion RAM. The units used are dots. Video or expansion RAM (SX, SY) →...
  • Page 82 Step 2: Select destination memory and direction from base coordinate R#45 MXD MSX 0: Right X transfer direction 1: Left 0: Down Y transfer direction 1: Up 0: VRAM Source location select 1: ExpRAM 0: VRAM Destination location select 1: ExpRAM Step 3: Define logical operation and execute the command R#46 LMMM cmd...

  • Page 83: Lmmv (Logical Move Vdp To Vram)

    4.4.8. LMMV (Logical move VDP to VRAM) LMMV command is used to paint in a specific rectangular area in the VRAM or expansion RAM. The units used are dots. Video or expansion RAM (DX, DY) → ↓ LMMV execution order Step 1: Set necessary coordinates in command registers R#36 DX: Destination...
  • Page 84 Step 3: Select destination memory and direction from base coordinate R#45 0: Right X transfer direction 1: Left 0: Down Y transfer direction 1: Up 0: VRAM Destination select 1: ExpRAM Step 4: Execute the command R#46 LMMV cmd Step 5: Check for command completion CPU should check CE bit of status register S#2 to identify if VDP has completed execution of the command.

  • Page 85: Line

    4.4.9. LINE LINE command is used to draw straight line in VRAM of expansion RAM. The line drawn is the hypotenuse of the triangle defined by the “long” and “short” sides. The distances are defined from the single starting point. Words “long” and “short” are used to identify respective sets of registers to use to define triangle’s sides: long side is defined in registers R#40 and R#41 (by 10 bits MJ9…MJ0 with value in the range 0…1023) and short side is defined in registers R#42 and R#43 (by 9 bits MI8…MI0 with value in the range...
  • Page 86 Step 2: Set color register value Color of the resulting line mask is coded in color register R#44 (CLR). Format of color data depends on the graphics mode. R#44 G4, G6 Step 3: Select destination memory, direction from base coordinate and orientation Bit MAJ of the register R#45 controls which coordinate is defined in registers R#40- R#43.

  • Page 87: Srch

    4.4.10. SRCH SRCH command is used to search for the specific color in VRAM of expansion RAM to the right or left of the starting point. The units used are dots. Video or expansion RAM (SX, SY) Border color point SRCH execution order Step 1: Set necessary coordinates in command registers R#32...
  • Page 88 R#45 0: NeqStop Stop condition 1: EqStop 0: Right X search 1: Left direction 0: VRAM Destination location select 1: ExpRAM Step 4: Execute the command R#46 SRCH cmd Step 5: Check for command termination or completion, and X-coordinate Flag BD of the status register S#2 is set if coded color in register R#44 was found, otherwise this bit is reset.
  • Page 89 Flowchart of SRCH execution from CPU point of view SRCH Start Set up VDP registers Execute command Read status register #2 No (CE=1) Command end? Yes (CE=0) No (BD=0) Color found? Yes (CE=0) Read status registers S#8 and S#9 SRCH End ©...

  • Page 90: Pset

    4.4.11. PSET PSET command is used to draw a dot in VRAM of expansion RAM. Programmer can select logical operation on the existing color of the dot in the specified location. The units used are dots. Video or expansion RAM (DX, DY) PSET execution order Step 1: Set necessary coordinates in command registers...
  • Page 91 Step 3: Select destination memory R#45 0: VRAM Destination location select 1: ExpRAM Step 4: Define logical operation and execute the command R#46 PSET cmd Logical operation Step 5: Check for command completion CPU should check CE bit of status register S#2 to identify if VDP has completed execution of the command.

  • Page 92: Point

    4.4.12. POINT POINT command is used to read the color of the specified dot located in VRAM of expansion RAM. The units used are dots. Video or expansion RAM (SX, SY) POINT execution order Step 1: Set necessary coordinates in command registers R#32 SX: Source R#33...

  • Page 93: Speeding Up The Processing Of Commands

    Step 4: Check for command completion CPU should check CE bit of status register S#2 to identify if VDP has completed execution of the command. When command is being executed, CE bit is set to 1; when command is complete, CE bit will be reset to 0. After completion of the command, source dot color code can be read from status register S#7.

  • Page 94: States Of The Registers After Command Execution

    4.6. States of the registers after command execution Setting up VDP registers for command execution is a significant task for programmer and CPU, and it will be wise to use already existing values in the registers for the next command execution or for further work with video memory. For this purpose programmer should know the resulting states of most important VDP registers.

  • Page 95: Sprites

    5. SPRITES MSX-VIDEO can display up to 32 sprites on the screen. Depending on the sprite mode, sprite sizes can be 8*8 or 16*16 dots. X-axis coordinate of sprite location is always between 0…255, and this means that in graphics modes with 512 dots on the X-axis single sprite’s dot occupy two horizontal dots of the screen.

  • Page 96: Sprite Mode 1 (G1, G2, Mc)

    5.1. SPRITE MODE 1 (G1, G2, MC) While there’s a room for 256 sprite patterns in sprite pattern generator table, VDP is only capable of displaying 32 sprites (#0…#31) – limiting factor is sprite attribute table active which can hold attributes for 32 sprites only.
  • Page 97 5.1.1. Global sprite attributes and tables (SM1) Register R#1 contains two controls for sprites, allowing magnification and quadruple sprite pattern size. Mode R#1 0: Normal Sprite 1: Double magnification 0: 8*8 Sprite size 1:16*16 Sprites are defined by two tables: sprite pattern generator table, which controls the appearance of the dots within the sprite (being on “1”...
  • Page 98 coordinate of 208 will not be displayed and in order to display sprite in this area on the scrolled screen programmer should use Y-coordinate equal to 207 or 209. Pattern number specifies which pattern from sprite pattern generator table to use to display the sprite bitmap image.
  • Page 99 5.1.4. Example of the sprite pattern generator table 8*8 sprite representation 16*16 sprite representation Offset 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 16*16 sprite size mode pattern layout Remember that in 16*16 sprite size mode two least significant bits of pattern number are not used, and setting sprite...

  • Page 100: Sprite Mode 2 (G3, G4, G5, G6, G7)

    5.2. SPRITE MODE 2 (G3 … G7) While there’s a room for 256 sprite patterns in sprite pattern generator table, VDP is only capable of displaying 32 sprites (#0…#31) – limiting factor is sprite attribute table active which can hold attributes for 32 sprites only.
  • Page 101 5.2.1. Global sprite attributes and tables (SM2) Register R#1 contains two controls for sprites, allowing magnification and quadruple sprite pattern size. Register R#8 contains one control bit, “SPD”, which allows disabling and enabling sprite display. 0: Normal Sprite 1: Double magnification 0: 8*8 Sprite size...
  • Page 102 Y-coordinate defines the vertical position of the sprite. Note that if Y is equal to 216 (D8h), all lower priority sprites will not be displayed. It is important to know that when using vertical offset register R#23 to scroll the visible area of the screen, sprite with the Y- coordinate of 216 will not be displayed and in order to display sprite in this area on the scrolled screen programmer should use Y=coordinate equal to 215 or 217.
  • Page 103 (B) 0 Bitmap for pattern #0 … 2040 2041 2042 2043 Bitmap for pattern #255 2044 2045 2046 2047 5.2.4. Sprite color table (SM2) In SPRITE MODE 2 (SM2) the sprite color table specifies sprite colors for each sprite line. Note that sprite color 0 (i.e. the dots having “0” for them in sprite pattern generator table) is transparent unless TP bit of register R#8 is set.
  • Page 104 Color code Line 1 Color code Line 2 Colors for sprite #0 Color code Line 16 … … Color code Line 1 Color code Line 2 Colors for sprite #31 Color code Line 16 Color code for each line (0…15) 0: Detect Line collision detect...
  • Page 105 Sprite #N Color code 8 CC = all set to 0 Sprite #N+1 Color code 4 CC = all set to 1 Sprite #N+2 Color code 2 CC = all set to 1 Resulting images in SM1 and SM2 modes (all sprites are placed at the same X, Y). Sprite mode 2: CC flag is used, no collision Sprite mode 1: collision detection detection...
  • Page 106 5.2.6. Sprite collision If CC bit is set to 0 and two sprites overlap with their color code 1 (the dots of two sprites defined by “1” in their bitmap), a sprite collision event occur, and bit 5 (“C”) of status register S#0 will be set to “1”.

  • Page 107: Special Rules For Sprite Color Settings

    5.3. Special rules for sprite color settings In all graphic modes except GRAPHIC7 mode, sprite display color is determined by the values in palette registers. In GRAPHIC7 mode sprite colors are fixed and are not related to contents of palette registers.

  • Page 108: Special Functions

    6. SPECIAL FUNCTIONS 6.1. Alternate display of two graphic screen pages Two graphics screen pages may be alternatively displayed in G4 to G7 modes automatically. In G4 and G5 modes, the following pages can be displayed alternatively: page 0 and page 1, and page 2 and page3. In G6 and G7 modes, pages 0 and 1 will be alternatively displayed.

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