Section 4 Exception Handling; Exception Handling Types And Priority; Exception Sources And Exception Vector Table; Table 4.1 Exception Types And Priority - Hitachi H8S/2628 Hardware Manual

4.1

Exception Handling Types and Priority

As shown in table 4.1, exception handling may be caused by a reset, trace, interrupt, or trap
instruction. Exception handling is prioritized as shown in table 4.1. If two or more exceptions
occur simultaneously, they are accepted and processed in order of priority. Exception sources, the
stack structure, and operation of the CPU vary depending on the interrupt control mode. For
details on the interrupt control mode, refer to section 5, Interrupt Controller.
Table 4.1 Exception Types and Priority
Priority Exception Type
High Reset
1
Trace*
Direct transition
Interrupt
Low Trap instruction *
Notes: 1. Traces are enabled only in interrupt control mode 2. Trace exception handling is not
executed after execution of an RTE instruction.
2. Interrupt detection is not performed on completion of ANDC, ORC, XORC, or LDC
instruction execution, or on completion of reset exception handling.
3. Trap instruction exception handling requests are accepted at all times in program
execution state.
4.2

Exception Sources and Exception Vector Table

Different vector addresses are assigned to different exception sources. Table 4.2 lists the exception
sources and their vector addresses. Since the usable modes differ depending on the product, for
details on each product, refer to section 3, MCU Operating Modes.

Section 4 Exception Handling

Start of Exception Handling
Starts immediately after a low-to-high transition at the RES
pin, or when the watchdog timer overflows. The CPU enters
the reset state when the RES pin is low.
Starts when execution of the current instruction or exception
handling ends, if the trace (T) bit in EXR is set to 1.
Starts when a direction transition occurs as the result of
SLEEP instruction execution.
Starts when execution of the current instruction or exception
handling ends, if an interrupt request has been issued.*
3
Started by execution of a trap instruction (TRAPA).
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