Operation In Asynchronous Mode; Data Transfer Format; Figure 14.2 Data Format In Asynchronous Communication (Example With 8-Bit Data, Parity, Two Stop Bits) - Hitachi H8S/2628 Hardware Manual

H8s/2628 series 16-bit single-chip microcomputer
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14.4

Operation in Asynchronous Mode

Figure 14.2 shows the general format for asynchronous serial communication. One frame consists
of a start bit (low level), followed by data (in LSB-first order), a parity bit (high or low level), and
finally stop bits (high level). In asynchronous serial communication, the transmission line is
usually held in the mark state (high level). The SCI monitors the transmission line. When the
transmission line goes to the space state (low level), the SCI recognizes a start bit and starts serial
communication. In asynchronous serial communication, the communication line is usually held in
the mark state (high level). The SCI monitors the communication line, and when it goes to the
space state (low level), recognizes a start bit and starts serial communication. Inside the SCI, the
transmitter and receiver are independent units, enabling full-duplex. Both the transmitter and the
receiver also have a double-buffered structure, so data can be read or written during transmission
or reception, enabling continuous data transfer.
1
LSB
Serial
0
data
Start
bit
1 bit
Figure 14.2 Data Format in Asynchronous Communication
14.4.1

Data Transfer Format

Table 14.10 shows the data transfer formats that can be used in asynchronous mode. Any of 12
transfer formats can be selected according to the SMR setting. For details on the multiprocessor
bit, refer to section 14.5, Multiprocessor Communication Function.
D0
D1
D2
D3
Transmit/receive data
7 or 8 bits
One unit of transfer data (character or frame)
(Example with 8-Bit Data, Parity, Two Stop Bits)
MSB
D4
D5
D6
D7
Parity
bit
1 bit,
or none
Idle state
(mark state)
1
0/1
1
1
Stop bit
1 or
2 bits
Rev. 1.0, 09/02, page 315 of 568

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