Mitsubishi Q00JCPU User Manual page 633

APPENDICES
Number Name Meaning
SD90
SD91
SD92
SD93
Step transition
watchdog timer
SD94
F number for timer
setting value
set value and time
(Enabled only
over error
SD95
when SFC
program exists)
SD96
SD97
SD98
SD99
Stores the
transmission
Transmission
speed specified in
SD100 speed storage
the serial
area
communication
setting.
Stores the
communication
Communication
setting specified in
SD101 setting storage
the serial
area
communication
setting.
Stores the
transmission wait
Transmission
time specifed in
SD102 wait time
the serial
storage area
communication
setting.
Stores the preset
CH1
transmission
transmission
SD105 speed when GX
speed setting
Developer is
(RS232)
used.
Stores the data
Data sending sending result
SD110 result storage when the serial
area communication
function is used.
Stores the data
Data receiving receiving result
SD111 result storage when the serial
area communication
function is used.
TableApp.18 Special register
Explanation
Corresponds to
SM90 • Set the annunciator number (F number) that will
be turned ON when the step transition watchdog
Corresponds to
timer setting or watchdog timer time limit error
SM91
occurs.
Corresponds to
SM92
b15 to
Corresponds to
SM93
Corresponds to
SM94
F number setting
Corresponds to
(0 to 255)
SM95
Corresponds to
SM96
Corresponds to
• Turning ON any of SM90 to SM99 during an
SM97
active step starts the timer, and if the transition
condition next to the corresponding step is not
Corresponds to
met within the timer time limit, the set
SM98
annunciator (F) turns ON.
Corresponds to
SM99
96 : 9.6kbps, 192 : 19.2kbps,
576 : 57.6kbps, 1152 : 115.2kbps
b15 b6
to
Online program correction setting
0: Disabled
1: Enabled
* : Since the data is used by the system, it is undefined.
0 : No waiting time
1 to F : Waiting time (unit: 10ms)
H
Defaults to 0.
3 : 300bps, 6 : 600bps,
48 : 4800bps, 96 : 9600bps,
384 : 38.4kbps, 576 : 57.6kbps,
The error code at data transmission is stored.
Stores the error code at the time of data receiving.
Set by
(When set)
b8 b7 to b0
Timer time limit
U
setting
(1 to 255s:
(1s units))
384 : 38.4kbps, S (Power-on or
reset)
b5 b4 b3 b0
to
S (Power-on or
reset)
Sumcheck yes/no
0: No
1: Yes
S (Power-on or
reset)
24 : 2400bps,
192 : 19.2kbps, S
1152 : 115.2kbps
S (Error)
S (Error)
Appendix 2 Special Register List
Corres-
ponding
Corresponding
ACPU
CPU
D9
D9108
D9109
D9110
D9111
QnA
D9112
Qn(H)
QnPH
D9113
QnPRH
D9114
New
New
New
New
New Q00/Q01
New
Qn(H)
QnPH
New
QnPRH
Rem
New Q00/Q01
App
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