Bus Operation - Motorola MC68824 User Manual

SECTION 6
BUS OPERATION
The following section describes the bus signal operation during data transfer operations, bus
exception conditions, host processor operations, OMA operations, and reset. Functional timing
diagrams are included to assist in the definition of signal timing; however, these diagrams are
not intended as parametric timing definitions. For detailed relatiQnships refer to
SECTION
8
ELEC-
TRICAL SPECIFICATIONS.
6.1 HOST PROCESSOR OPERATION MODE
In the host processor operation mode or slave mode, the TBC is a peripheral slave to the bus
master. The TBC enters the slave mode when chip select (CS) or interrupt acknowledge (lACK) is
asserted. Ouring host processor operations, the TBC places data onto the data bus or accepts
data from the data bus, respectively, according to the level of the RIW pin. This mode of operation
is used during TBC initialization to load the configuration information and initial parameters into
the TBC. After initialization, the slave mode of operation is used by the host processor to place
commands into the TBC command register.
The TBC can operate with a ClK input that is either synchronous or asynchronous with respect
to the host processor clock provided the bus requirements are satisfied. The timing diagrams
assume that an M68000 Family processor is the host processor with a clock signal identical to
the TBe ClK.
6.1.1
Host Processor Read Cycles
Ouring the host processor read cycle, the bus master asserts chip select (CS), read (RIW) and
lower data strobe (lOS/OS). The TBC then places data onto the data bus and asserts data transfer
acknowledge (OTACK) to indicate to the bus master that the data is valid. The semaphore register
will always be selected on a read cycle regardless of A 1 and A2 encodings because it is the only
readable register. When the lower data strobe (lOS/OS), or chip select (CS), is negated by the
host, the TBC will three-state the data lines and then negate and three-state OTACK. This is shown
in Figure 6-1. The timing for even and odd byte host reads on a 16-bit data bus or any host read
on an 8-bit data bus are identical. The encodings of UOS/AO and lOS/OS select the proper byte.
6.1.2 Host Processor Write Cycles
Ouring host processor write cycles, the TBC accepts data from the data bus and asserts OTACK
to indicate to the bus master that the data has been loaded into the selected register. The only
TBC registers that are directly writable by the host processor are the command register, the upper
six bits of the interrupt vector register, and the data register. .
To begin a host processor write cycle, the bus master asserts CS and drives RIW low. The TBC
responds by decoding the A1, A2, UOS/AO, and lOS/OS signals. When a valid register (CR, OR,
MC68824 USER'S MANUAL MOTOROLA
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