Addv - Hitachi SH7750 Programming Manual

High-performance risc engine superh (sh) 32-bit risc mcu/mpu series
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10.3

ADDV

Binary Addition
with Overflow Check
Format
ADDV Rm,Rn
Description
This instruction adds together the contents of general registers Rn and Rm and stores the result in
Rn. If overflow occurs, the T bit is set.
Operation
ADDV(long m, long n)
{
long dest,src,ans;
if ((long)R[n]>=0) dest=0;
else dest=1;
if ((long)R[m]>=0) src=0;
else src=1;
src+=dest;
R[n]+=R[m];
if ((long)R[n]>=0) ans=0;
else ans=1;
ans+=dest;
if (src==0 || src==2) {
if (ans==1) T=1;
else T=0;
}
else T=0;
PC+=2;
}
ADD with (V flag) overflow check Arithmetic Instruction
Summary of Operation
Rn+Rm → Rn,
overflow → T
/* ADDV Rm,Rn */
Instruction Code
0011nnnnmmmm1111 1
Rev. 2.0, 03/99, page 203 of 396
Execution
States
T Bit
Overflow

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