Hitachi SH7750 Programming Manual page 192

Table 9.1 Status of CPU and Peripheral Modules in Power-Down Modes
Power-
Down Entering
Mode Conditions CPG
Sleep SLEEP
instruction
executed
while STBY
bit is 0 in
STBCR
Deep SLEEP
sleep instruction
executed
while STBY
bit is 0 in
STBCR,
and DSLP
bit is 1 in
STBCR2
Standby SLEEP
instruction
executed
while STBY
bit is 1 in
STBCR
Module Setting
standby MSTP bit to
1 in STBCR
Note: The RTC operates when the START bit in RCR2 is 1 (see section 11, Realtime Clock
(RTC), in the Hardware Manual).
Rev. 2.0, 03/99, page 178 of 396
CPU
Operating Halted
(registers
held)
Operating Halted
(registers
held)
Halted Halted
(registers
held)
Operating Operating Held
Status
On-chip
On-Chip Peripheral
Memory Modules
Held Operating
Held Operating
(DMA
halted)
Held Halted*
Specified
modules
halted*
External Exiting
Pins Memory Method
Refreshing • Interrupt
Held
• Reset
• Interrupt
Held Self-
refreshing
• Reset
• Interrupt
Held Self-
refreshing
• Reset
Refreshing • Clearing
Held
• Reset
MSTP bit
to 0