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QQ
3 7 63 1515 0
IC806,807 EM636165TS,KM416S1120DT,K4S161622D (1 Mega x 16 Synchronous DRAM)
Pin
CLK
CS
CKE
A0~A10/AP
BA
RAS
CAS
TE
L 13942296513
WE
L(U)DQM
DQ0~15
V
/V
DD
V
DDQ
N.C/RFU
IC811 PQ025EZ01ZPN (Low Voltage Operation Low
Power-Loss VoltageRegulators)
1
2
3
www
.
http://www.xiaoyu163.com
Name
System Clock
Chip Select
Clock Enable
Address
Bank Select Address
Row Address Strobe
Column Address Strobe
Write Enable
Data Input/Output Mask
Data Input/Output
Power Supply/Ground
SS
/V
Data Output Power/Ground
SSQ
No Connection/
Reserved for Future Use
1
Specific IC
5
1 DC input (V
)
IN
2 ON/OFF control terminal (V
3 DC output (V
)
O
4 NC
4
5
5 GND
x
ao
y
i
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8
MPEG P.C.B.
Input Function
Active on the positive going edge to sample all inputs.
Disables or enable device operation by masking or enabling all inputs except
CLK,CKE and L(U)DQM
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least ono cycle prior to new command.
Disable input buffers for power down in standby.
Row / column addresses are multiplexed on the same pins.
Row address : RA0~RA10, column address : CA0~CA7
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
Q Q
3
6 7
1 3
Enables write operation and row precharge.
Latches data in standing from CAS, WE active.
Makes data output Hi-Z, t
after the clock and masks the output.
SHZ
Blocks data input when L(U)DQM active.
Data inputs/outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide improved noise
immunity.
This pin is recommended to be left No Connection on the device.
IC812 PST3627UR (Reset IC)
2
V
DD
3
2
Vref
)
C
GND
1
GND 1
u163
V
2
DD
.
DVR-S60/NX-SW60
2 9
9 4
2 8
1 5
0 5
8
2 9
9 4
R
D
3
C
D
m
PIN No.
PIN NAME
FUNCTIONS
OUT
4
1
GND
GND Pin
co
2
V
V
Pin / Voltage Detect Pin
DD
DD
3
C
Capacitor Connect Pin with Delay
D
3
C
D
4
OUT
Reset Signal Output Pin
9 9
2 8
9 9
4
OUT
55
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