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DVR-S60/NX-SW60
QQ
3 7 63 1515 0
IC871,881 LE28DW8102T-90-MPB (Flash Memory)
1
A15
2
A14
3
A13
4
A12
5
A11
6
A10
7
A9
8
A8
9
WE#
10
NC
11
NC
12
NC
13
NC
14
NC
15
NC
16
A18
17
A17
18
A78
19
A6
20
A5
21
A4
22
A3
23
A2
24
ACE#
Symbol
A18
A17-A0
A17-A15
A17-A10
DQ15-DQ0
CE#
OE#
WE#
TE
L 13942296513
VDD
GND
NC
IC804,805 TC74LCX373FT (Low Voltage Octal D-type Latch with 5V Tolerant Inputs and Outputs)
OE
Q0
D0
D1
Q1
Q2
D2
D3
Q3
GND
LE
www
OE
.
54
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MPEG P.C.B.
48
A16
47
VSS
Charge Pump
46
DQ15
&
45
DQ7
44
Constant Voltage
DQ14
43
DQ6
Circuit
42
DQ13
41
DQ5
40
DQ12
Address Buffer
39
DQ4
38
NC
Latch Circuit
37
VDD
36
DQ11
35
DQ3
34
DQ10
A18-A0
33
DQ2
32
DQ9
31
DQ1
CE#
30
DQ8
OE#
29
DQ0
28
WE#
OE#
27
VSS
26
A0
25
A1
Description
Select Bank 1 (negative) or Bank 2 (positive)
Bank select address
Flash bank address
Flash bank address during write
Flash bank block address
Select at flash bank for erase
Flash bank selector address
Select at flash bank sector for erase
Data input/output
Output the data during read cycle and receive the input data
during write cycle
Chip enable
Enable the data flash bank when CE# is negative
Output enable
Enable the data output buf fer
Write enable
Write, Erase, Program control
Power supply
Power supply (2.07V~3.6V)
Ground
Ground
No connect
No connect
1
20
V
CC
2
19
Q7
3
18
D7
4
17
D6
5
16
Q6
6
15
Q5
7
14
D5
8
13
D4
9
12
Q4
10
11
LE
Truth Table
D0
D1
D2
3
4
7
D
D
D
Q
Q
L
L
11
1
x
ao
y
2
5
Q0
Q1
i
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8
Column Decoder
&
Low Decoder
DQ15.DQ0
Control Logic
Function
Q Q
3
6 7
1 3
INPUTS
OE
LE
D
H
X
X
L
L
X
L
H
L
L
H
H
X : Don't Care
Z : High impedance
Qn : Q Output level before LE turn into "L"
D3
D4
D5
8
13
14
D
D
D
Q
Q
Q
Q
L
L
L
L
u163
6
9
12
Q2
Q3
Q4
Q5
.
2 9
9 4
2 8
256Kx16
Flash
Bank 1
256Kx16
Flash
Bank 2
Input/Output
Buffer Data Latch
1 5
0 5
8
2 9
OUTPUTS
Z
Qn
L
H
D7
D6
18
17
D
D
Q
Q
L
L
m
co
19
15
16
Q7
Q6
9 9
9 4
2 8
9 9
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