Toshiba TLCS-900/H1 Series Manual page 434

3.20.2 SFR
The following tables show the SFR for I
data bus. When the CPU accesses the SFR, use a 2-byte load instruction.
I2SCTL0 Bit symbol
(080EH)
Read/Write
Reset State
Function
Note: <I2SWCK> is effective only for I
(080FH) Bit symbol
Read/Write
Reset State
Function
Note: <I2SWLVL>, <I2FSEL> and <I2SCLKE> are effective only in I
I2SBUFR Bit symbol
(0800H)
Read/Write
Read-modify-
Reset State
write
instruction is Function
prohibited
I2SBUFL Bit symbol
(0808H)
Read/Write
Read-modify-
Reset State
write
instruction is Function
prohibited
7 6
TXE FMT
R/W
0 0
Transmit Mode Status
2
0: Stop
0: Stop 0: I S
1: Under
1: Start 1: SIO
2
15 14
I2SWLVL EDGE I2SFSEL
R/W
0 0
WS level Clock edge Select for
0: Low left for data out stereo
1: High left 0: Falling 0: Stereo
1: Rising
1: Monaural
I2SBUFR Register
15 14 13 12 11
R15 R14 R13 R12 R11
Register for transmitting buffer (FIFO) (Right channel)
15 14 13 12 11
L15 L14 L13 L12 L11
Register for transmitting buffer (FIFO) (Left channel)
Figure 3.20.2 I
S. This I S is connected to the CPU by the 16-bit
2 2
I2SCTL0 Register
5 4
BUSY DIR
R
0 0
First bit Bit number
0: MSB 0: 8 bits
1: LSB 1: 16 bits
transmitting
S mode.
13 12
I2SCLKE
0 0
Clock
enable
(After
transmit)
(2 channels)
0: Operation
1: Stop
(1 channel)
10 9 8 7
R10 R9 R8 R7
W
Undefined
I2SBUFL Register
10 9 8 7
L10 L9 L8 L7
W
Undefined
2
S SFR
92CH21-432
3 2 1
BIT MCK1 MCK0
R/W
0 0 0
Baud rate
00: f 10: f
SYS SYS
01: f /2 11: f
SYS SYS
11 10 9
2
S mode.
6 5 4 3
R6 R5 R4 R3
6 5 4 3
L6 L5 L4 L3
TMP92CH21
0
I2SWCK
0
WS clock
/4 0: fs/4
/8 1: TA1OUT
8
SYSCKE
R/W
0
System
clock
0: Disable
1: Enable
2 1 0
R2 R1 R0
2 1 0
L2 L1 L0
2009-06-19