Toshiba TLCS-900/H1 Series Manual page 411

TMP92CH21
3.17.5 Timing Diagrams
3.17.5.1 Command and Address Cycle
ND0FMCR<ALE> = 0
ND0FMCR<CLE> = 0
ND0FMCR<ALE> = 1
ND0FMCR<CLE> = 1
ND0FMCR<CE> = 1
Figure 3.17.10 Command and Address Cycle
2009-06-19
92CH21-409