Philips LPC2119 User Manual page 185

Philips Semiconductors
ARM-based Microcontroller
Capture Registers (CR0 - CR3)
Each Capture register is associated with a device pin and may be loaded with the Timer Counter value when a specified event
occurs on that pin. The settings in the Capture Control Register register determine whether the capture function is enabled, and
whether a capture event happens on the rising edge of the associated pin, the falling edge, or on both edges.
Capture Control Register (CCR: TIMER0 - T0CCR: 0xE0004028; TIMER1 - T1CCR: 0xE0008028)
The Capture Control Register is used to control whether one of the four Capture Registers is loaded with the value in the Timer
Counter when the capture event occurs, and whether an interrupt is generated by the capture event. Setting both the rising and
falling bits at the same time is a valid configuration, resulting in a capture event for both edges. In the description below, "n"
represents the Timer number, 0 or 1.
Table 160: Capture Control Register (CCR: TIMER0 - T0CCR: 0xE0004028; TIMER1 - T1CCR: 0xE0008028)
CCR Function
Capture on CAPn.0
0
rising edge
Capture on CAPn.0
1
falling edge
Interrupt on CAPn.0
2
event
Capture on CAPn.1
3
rising edge
Capture on CAPn.1
4
falling edge
Interrupt on CAPn.1
5
event
Capture on CAPn.2
6
rising edge
Capture on CAPn.2
7
falling edge
Interrupt on CAPn.2
8
event
Capture on CAPn.3
9
rising edge
Capture on CAPn.3
10
falling edge
Interrupt on CAPn.3
11
event
Timer0 and Timer1
When one, a sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with
the contents of the TC. When zero, this feature is disabled.
When one, a sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with
the contents of TC. When zero, this feature is disabled.
When one, a CR0 load due to a CAPn.0 event will generate an interrupt. When
zero, this feature is disabled.
When one, a sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with
the contents of the TC. When zero, this feature is disabled.
When one, a sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with
the contents of TC. When zero, this feature is disabled.
When one, a CR1 load due to a CAPn.1 event will generate an interrupt. When
zero, this feature is disabled.
When one, a sequence of 0 then 1 on CAPn.2 will cause CR2 to be loaded with
the contents of the TC. When zero, this feature is disabled.
When one, a sequence of 1 then 0 on CAPn.2 will cause CR2 to be loaded with
the contents of TC. When zero, this feature is disabled.
When one, a CR2 load due to a CAPn.2 event will generate an interrupt. When
zero, this feature is disabled.
When one, a sequence of 0 then 1 on CAPn.3 will cause CR3 to be loaded with
the contents of TC. When zero, this feature is disabled.
When one, a sequence of 1 then 0 on CAPn.3 will cause CR3 to be loaded with
the contents of TC. When zero, this feature is disabled.
When one, a CR3 load due to a CAPn.3 event will generate an interrupt. When
zero, this feature is disabled.
LPC2119/2129/2292/2294
Description
185
Preliminary User Manual
Reset
Value
0
0
0
0
0
0
0
0
0
0
0
0
January 08, 2004