Philips LPC2119 User Manual page 131

Philips Semiconductors
ARM-based Microcontroller
UART1 Line Status Register (U1LSR - 0xE0010014, Read Only)
The U1LSR is a read-only register that provides status information on the UART1 Tx and Rx blocks.
Table 98: UART1 Line Status Register Bit Descriptions (U1LSR - 0xE0010014, Read Only)
U1LSR Function
Receiver Data
0
Ready (RDR)
Overrun Error
1
(OE)
2 Parity Error (PE)
Framing Error
3
(FE)
Break Interrupt
4
(BI)
Transmitter
5 Holding Register
Empty (THRE)
Transmitter
6
Empty (TEMT)
Error in Rx FIFO
7
(RXFE)
UART1
0: U1RBR is empty
1: U1RBR contains valid data
U1LSR0 is set when the U1RBR holds an unread character and is cleared when the
UART1 RBR FIFO is empty.
0: Overrun error status is inactive.
1: Overrun error status is active.
The overrun error condition is set as soon as it occurs. An U1LSR read clears U1LSR1.
U1LSR1 is set when UART1 RSR has a new character assembled and the UART1 RBR
FIFO is full. In this case, the UART1 RBR FIFO will not be overwritten and the character
in the UART1 RSR will be lost.
0: Parity error status is inactive.
1: Parity error status is active.
When the parity bit of a received character is in the wrong state, a parity error occurs. An
U1LSR read clears U1LSR2. Time of parity error detection is dependent on U1FCR0.
A parity error is associated with the character being read from the UART1 RBR FIFO.
0: Framing error status is inactive.
1: Framing error status is active.
When the stop bit of a received character is a logic 0, a framing error occurs. An U1LSR
read clears this bit. The time of the framing error detection is dependent on U1FCR0.
A framing error is associated with the character being read from the UART1 RBR FIFO.
Upon detection of a framing error, the Rx will attempt to resynchronize to the data and
assume that the bad stop bit is actually an early start bit.
0: Break interrupt status is inactive.
1: Break interrupt status is active.
When RxD1 is held in the spacing state (all 0's) for one full character transmission (start,
data, parity, stop), a break interrupt occurs. Once the break condition has been detected,
the receiver goes idle until RxD1 goes to marking state (all 1's). An U1LSR read clears
this status bit. The time of break detection is dependent on U1FCR0.
The break interrupt is associated with the character being read from the UART1 RBR
FIFO.
0: U1THR contains valid data.
1: U1THR is empty.
THRE is set immediately upon detection of an empty U1THR and is cleared on a U1THR
write.
0: U1THR and/or the U1TSR contains valid data.
1: U1THR and the U1TSR are empty.
TEMT is set when both THR and TSR are empty; TEMT is cleared when either the
U1TSR or the U1THR contain valid data.
0: U1RBR contains no UART1 Rx errors or U1FCR0=0.
1: U1RBR contains at least one UART1 Rx error.
U1LSR7 is set when a character with a Rx error such as framing error, parity error or
break interrupt, is loaded into the U1RBR. This bit is cleared when the U1LSR register is
read and there are no subsequent errors in the UART1 FIFO.
LPC2119/2129/2292/2294
Description
131
Preliminary User Manual
Reset
Value
0
0
0
0
0
1
1
0
January 08, 2004