Variable-Latency Io Access Cycles - Epson S1D13706 Technical Manual

Epson Research and Development
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2.1.3 Variable-Latency IO Access Cycles

A[25:0]
nCS4
nOE
nWE
RDY
D[31:0]
nCAS[3:0]
Interfacing to the Intel StrongARM SA-1110 Microprocessor
Issue Date: 02/06/26
The first nOE assertion occurs two memory cycles after the assertion of chip select (nCS3,
nCS4, or nCS5). Two memory cycles prior to the end of minimum nOE or nWE assertion
(RDF+1 memory cycles), the SA-1110 starts sampling the data ready input (RDY).
Samples are taken every half memory cycle until three consecutive samples (at the rising
edge, falling edge, and following rising edge of the memory clock) indicate that the IO
device is ready for data transfer. Read data is latched one-half memory cycle after the third
successful sample (on falling edge). Then nOE or nWE is deasserted on the next rising edge
and the address may change on the subsequent falling edge. Prior to a subsequent data
cycle, nOE or nWE remains deasserted for RDN+1 memory cycles. The chip select and
byte selects (nCAS[1:0] for 16-bit data transfers), remain asserted for one memory cycle
after the final nOE or nWE deassertion of the burst.
The SA-1110 is capable of burst cycles during which the chip select remains low while the
read or write command is asserted, precharged and reasserted repeatedly.
Figure 2-1: illustrates a typical variable-latency IO access read cycle on the SA-1110 bus.
Figure 2-1: SA-1110 Variable-Latency IO Read Cycle
ADDRESS VALID
DATA VALID
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