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Epson SED1352 manual available for free PDF download: Technical Manual
Epson SED1352 Technical Manual (242 pages)
Graphics LCD Controller
Brand:
Epson
| Category:
Controller
| Size: 1.11 MB
Table of Contents
Section 1
33
Table of Contents
33
Overview Description
39
Introduction
39
Scope
39
Technology
40
System
40
Display Modes
40
Features
40
Display Support
41
Power Management
41
Typical System Block Diagrams
42
16-Bit MC68000 MPU
42
Figure 1: 16-Bit 68000 Series
42
MPU with READY (or WAIT#) Signal
43
Figure 2: 8-Bit Mode, Example: Z80
43
Figure 3: 16-Bit Mode, Example: I8086 (Maximum Mode)
43
Figure 5: 16-Bit Mode (ISA)
44
ISA Bus
44
Figure 4: 8-Bit Mode (ISA)
44
Internal Block Diagram
45
Functional Block Descriptions
45
Bus Signal Translation
45
Control Registers
45
Sequence Controller
45
LCD Panel Interface
45
Figure 6: Internal Block Diagram
45
SRAM Interface
46
Clock Inputs / Timing
46
CPU / CRT Selector
46
Display Data Formatter
46
Memory Decoder
46
Address Generator
46
Data Bus Conversion
46
Port Decoder
46
Look-Up Table
46
Pinout Diagram
47
Figure 7: SED1352F0B Pinout Diagram
47
Figure 8: SED1352F1B Pinout Diagram
48
Figure 9: SED1352D0B Pad Diagram
49
Table 4-1: SED1352D0A Pad Coordinates
50
Pinout Description
52
Table 5-1: Bus Interface
52
Table 5-2: Display Memory Interface
53
Table 5-3: LCD Interface
54
Table 5-4: Clock Inputs
54
Table 5-5: Power Supply
54
Table 5-6: Summary of Power on / Reset Options
55
Table 5-7: I/O and Memory Addressing Example
55
Table 6-1: Absolute Maximum Ratings
56
Table 6-2: Recommended Operating Conditions
56
Table 6-3: Input Specifications
56
Table 6-4: Output Specifications
57
Table 7-1: IOW# Timing (68000)
58
Figure 10: IOW# Timing (68000)
58
Figure 11: IOR# Timing (68000)
59
Table 7-2: IOR# Timing (68000)
59
Figure 12: MEMW# Timing (68000)
60
Table 7-3: MEMW# Timing (68000)
60
Table 7-4: MEMR# Timing (68000)
61
Figure 13: MEMR# Timing (68000)
61
Non-68000, Mpu/Bus with READY (or WAIT#) Signal
62
Table 7-5: IOW# Timing (Non-68000)
62
Figure 14: IOW# Timing (Non-68000)
62
Table 7-6: IOR# Timing (Non-68000)
63
Figure 15: IOR# Timing (Non-68000)
63
Table 7-7: MEMW# Timing (Non-68000)
64
Figure 16: MEMW# Timing (Non-68000)
64
Table 7-8: MEMR# Timing (Non-68000)
65
Figure 17: MEMR# Timing (Non-68000)
65
Figure 18: Clock Input Requirements
66
Figure 19: Recommended Clock Interface
66
Clock Input Requirements
66
Table 7-9: Clock Input Requirements
66
Recommended Clock Input
66
Display Memory Interface Timing
67
Write Data to Display Memory
67
Table 7-10: Write Data to Display Memory
67
Figure 20: Write Data to Display Memory
67
Read Data from Display Memory
68
Table 7-11: Read Data from Display Memory
68
Figure 21: Read Data from Display Memory
68
LCD Interface Timing
69
Figure 22: LCD Interface Timing
69
4-Bit Single LCD Interface Timing
70
Table 7-12: 4-Bit Single LCD Interface Timing
70
Table 7-13: 8-Bit LCD Interface Timing
71
8-Bit LCD Interface Timing
71
Figure 23: LCD Interface Pixel/Data Position
72
Figure 24: 4-Bit Single Monochrome Panel Timing
73
Figure 25: 8-Bit Single Monochrome Panel Timing
74
Figure 26: 8-Bit Dual Monochrome Panel Timing
75
Hardware Register Interface
76
Register Descriptions
76
Table 8-1: Maximum Value of Line Byte Count Register - 8-Bit Display Memory Interface
78
Table 8-2: Maximum Value of Line Byte Count Register - 16-Bit Display Memory Interface
78
Table 8-3: Power Save Mode Selection
79
Table 8-4: ID Bit Usage
83
Figure 27: 4-Level Gray-Shade Mode Look-Up Table Architecture
84
Look-Up Table Architecture
84
4-Level Gray Shade Mode
84
16-Level Gray Shade Mode
85
Power Save Modes (PSM 1)
85
Power Save Mode 1 (PSM1)
85
Table 8-5: Power Save Mode Selection
85
Figure 28: 16-Level Gray-Shade Mode Look-Up Table Architecture
85
Power Save Mode 2 (PSM2)
86
Power Save Mode Function Summary
86
Pin States in Power Save Modes
86
Table 8-6: Power Save Mode Function Summary
86
Table 8-7: Pin States in Power Save Modes
86
Figure 29: 8-Bit Mode - 8K Bytes SRAM
87
Figure 30: 8-Bit Mode - 16K Bytes SRAM
87
8-Bit Mode
87
SRAM Configurations Supported
87
Display Memory Interface
87
Figure 32: 8-Bit Mode - 40K Bytes SRAM
88
Figure 31: 8-Bit Mode - 32K Bytes SRAM
88
16-Bit Mode
89
Figure 33: 8-Bit Mode - 64K Bytes SRAM
89
Figure 34: 16-Bit Mode - 16K Bytes SRAM
89
Figure 35: 16-Bit Mode - 64K Bytes SRAM
90
Figure 36: 16-Bit Mode - 128K Bytes SRAM
90
For Dual Panel
91
Table 9-2: 16-Bit Display Memory Interface SRAM Access Time
91
Table 9-1: 8-Bit Display Memory Interface SRAM Access Time
91
Memory Size Calculation
91
For Single Panel
91
Frame Rate Calculation
91
8-Bit Display Memory Interface
91
SRAM Access Time
91
Memory Size Requirement
92
Table 9-3: Memory Size Requirement: Number of Horizontal Pixels = 640
92
Table 9-4: Memory Size Requirement: Number of Horizontal Pixels = 480
93
Table 9-5: Memory Size Requirement: Number of Horizontal Pixels = 320
93
Mechanical Data
94
Figure 37: Mechanical Drawing QFP5-100Pin-S2
94
Figure 38: Mechanical Drawing QFP15-100Pin
95
Section 2
99
Introduction
103
Initializing the Sed1352
104
Four Bit Pixels
111
Gray Shades and Look-Up Tables
111
Pixels
111
Two Bit Pixels
111
Look-Up Table (LUT)
112
LUT Registers
112
Look-Up Table Description
113
Four Gray Shades (Two Bits/Pixel)
115
Sixteen Gray Shades (Four Bits/Pixel)
117
Display Memory Models
118
Registers
118
Description
120
Sdu1352B0X Evaluation Board Display Memory
120
Display Start Address Registers
121
Common Display Memory Requirements for LCD Panel Sizes
123
Advanced Techniques
124
Registers
124
Virtual Displays
124
Description
125
Bitmaps and Text Displays
126
Direct Addressing
128
Indexed Addressing
128
Registers
128
Registers
130
Split Screen
130
Description
131
Single Panel LCD
131
Dual Panel LCD
134
Initialization
138
Panning and Scrolling
138
Panning Right and Left
138
Scrolling up and down
138
Power Save Modes
140
Power Saving
140
Registers
140
Programming the Sed1352
142
Main Loop Code
143
Initialization Code
144
Advanced Functions
148
Glossary
161
Section 3
189
Features
193
Sdu1352B0C Rev 1.0 Evaluation Board
193
Installation and Configuration
194
ISA Bus Support
198
Technical Description
198
Adjustable LCD Panel Negative Power Supply
199
Monochrome LCD Support
199
Non-ISA Bus Support
199
Power Save Modes
199
SRAM Support
199
Adjustable LCD Panel Positive Power Supply
200
Cpu/Bus Interface Header Strips
200
Crystal Support
200
Schematic Notes
200
Appendix Aparts LIST
201
Appendix Bsdu1352B0C REV. 1.0 SCHEMATIC DIAGRAMS
202
Section 4
215
Introduction
217
Reference Material
217
16-Bit Isa Bus Interface
218
Additional Discrete Logic Description
219
Configuration Options
219
PAL Equations
219
Register Setting
219
SED1352F0B Default Setup
219
8-Bit Isa Bus Interface
220
Configuration Options
221
Register Setting
221
SED1352F0B Default Setup
221
Introduction
227
Reference Material
227
Mc68340 Mpu Interface
228
MC68340 Setup
228
PAL Equations
229
SED1352 Default Setup
229
Section 5
233
Introduction
235
Reference Material
235
Configuration Equations
236
Example
236
Input Clock Requirement
236
SRAM Size
236
SRAM Size and Access Time Requirements
236
SRAM Access Time
237
8-Bit Display Memory Interface
238
Configuration Options
238
Implementation
238
Register Settings
239
16-Bit Display Memory Interface
240
Configuration Options
240
Register Settings
241
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