Clocks Tab - Epson S1D13706 Technical Manual

Embedded memory lcd controller
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Clocks Tab

CLKI
CLKI2
BCLK Source
BCLK Divide
S1D13706
X31B-B-001-03
PCLK Source
MCLK Source
The Clocks tab is intended to simplify the selection of input clock frequencies and the
source of internal clocking signals. For further information regarding clocking and clock
sources, refer to the S1D13706 Hardware Functional Specification, document number
X31B-A-001-xx.
In automatic mode the values for CLKI and CLKI2 are calculated based on selections made
for LCD timings from the Panel tab. In this mode, the required frequencies for the input
clocks are displayed in blue in the "Auto" section of each group. It is the responsibility of
the system designer to ensure that the correct CLKI frequencies are supplied to the
S1D13706.
Making a selection other than "Auto" indicates that the values for CLKI or CLKI2 are
known and are fixed by the system design. Options for LCD frame rates are limited to
ranges determined by the clock values.
Note
Changing clock values may modify or invalidate Panel settings. Confirm all settings on
the Panel tab after modifying any clock settings.
Epson Research and Development
Vancouver Design Center
PCLK Divide
MCLK Divide
13706CFG Configuration Program
PWMCLK Enable
PWMCLK
Force High
PWMCLK Source
PWMCLK Divide
PWMCLK
Duty Cycle
CV Pulse Enable
CV Pulse
Force High
CV Pulse Divide
CV Pulse
Burst Length
Issue Date: 01/03/29

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