5.7.3.10 BIT MANIPULATION INSTRUCTIONS. The bit manipulation instruction table
indicates the number of clock periods needed for the processor to perform the specified
operation on the given addressing mode. The total number of clock cycles is outside the
parentheses. The numbers inside parentheses (r/p/w) are included in the total clock cycle
number. All timing data assumes two-clock reads and writes.
BCHG
#, Dn
BCHG
Dn, Dm
BCHG
#, FEA
BCHG
Dn, FEA
BCLR
#, Dn
BCLR
Dn, Dm
BCLR
#, FEA
BCLR
Dn, FEA
BSET
#, Dn
BSET
Dn, Dm
BSET
#, FEA
BSET
Dn, FEA
BTST
#, Dn
BTST
Dn, Dm
BTST
#, FEA
BTST
Dn, FEA
An # fetch EA time must be added for this instruction: FEA
MOTOROLA
Freescale Semiconductor, Inc.
Instruction
MC68340 USER'S MANUAL
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Head
Tail
2
0
4
0
1
2
2
2
2
0
4
0
1
2
2
2
2
0
4
0
1
2
2
2
2
0
2
0
1
0
2
0
FEA
OPER
Cycles
6(0/2/0)
6(0/1/0)
8(0/2/1)
8(0/1/1)
6(0/2/0)
6(0/1/0)
8(0/2/1)
8(0/1/1)
6(0/2/0)
6(0/1/0)
8(0/2/1)
8(0/1/1)
4(0/2/0)
4(0/1/0)
4(0/2/0)
8(0/1/0)
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