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4.3.5.2 PORT A PIN ASSIGNMENT REGISTER 2 (PPARA2). PPARA2 selects between
an address and IACK function for the port A pins. Any set bit defines the corresponding
pin to be an IACK output pin. Any cleared bit defines the corresponding pin to be an
address bit as defined in the register diagram. Any set bits in PPARA1 override the
configuration set in PPARA2. Bit 0 has no function in this register because there is no
level 0 interrupt. This register can be read or written at any time.
The IACK signals are asserted if a bit in PPARA2 is set and the CPU32 services an
external interrupt at the corresponding level. IACK
address strobes.
Upon reset, port A is configured as an input port.
4.3.5.3 PORT A DATA DIRECTION REGISTER (DDRA). DDRA controls the direction of
the pin drivers when the pins are configured as I/O. Any set bit configures the
corresponding pin as an output. Any cleared bit configures the corresponding pin as an
input. This register affects only pins configured as discrete I/O. This register can be read
or written at any time.
4.3.5.4 PORT A DATA REGISTER (PORTA). PORTA affects only pins configured as
discrete I/O. A write to PORTA is stored in the internal data latch, and if any port A pin is
configured as an output, the value stored for that bit is driven on the pin. A read of PORTA
returns the value at the pin only if the pin is configured as discrete input. Otherwise, the
value read is the value stored in the internal data latch. This register can be read or written
at any time.
4-34
Freescale Semiconductor, Inc.
PPARA2
7
6
5
4
IACK7
IACK6
IACK5
IACK4
(A31)
(A30)
(A29)
(A28)
RESET:
0
0
0
0
NOTE:
DDRA
7
6
5
4
DD7
DD6
DD5
DD4
RESET:
0
0
0
0
PORTA
7
6
5
4
P7
P6
P5
P4
RESET:
U
U
U
U
MC68340 USER'S MANUAL
For More Information On This Product,
Go to: www.freescale.com
$017
3
2
1
0
IACK3
IACK2
IACK1
0
(A27)
(A26)
(A25)
0
0
0
0
Supervisor Only
signals have the same timing as
$013
3
2
1
0
DD3
DD2
DD1
DD0
0
0
0
0
Supervisor/User
$011
3
2
1
0
P3
P2
P1
P0
U
U
U
U
Supervisor/User
MOTOROLA
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