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Logic Symbology
:
~ ~
--FF-i-___
~
7900 124
Figure A-19. J-K Flip-Flop Logic Symbol
A-46.
CLOCKED J-K FLIP-FLOP. The clocked J-K flip-
flop as shown in figure A-20 is similar to the clocked R-S
flip-flop. However, simultaneous set and clear inputs to the
J-K flip-flop are permissible. Under these conditions, the
J-K flip-flop changes its state at the occurrence of each
positive-going clock pulse transition. With an inverting dot
at the clock pulse input, the flip-flop changes state at the
negative-going clock pulse transition. If both J and K inputs
are high, the flip-flop will toggle when a clock pulse is
received.
A
t~
I
FF
Q
C
B
Q
INPUT
INITIAL
FINAL
OUTPUT"
OUTPUT""
A
B
Q
I
Q
Q
I
H
H
L
.1
H
H
I
H
H
H
L
L
L
L
Either
No Change
H
L
Either
H
I
L
H
Either
L
"Before clock pulse transition.
"" After clock pulse transition.
7900··125
Figure A-20. Clocked J-K Flip-Flop Logic
Symbol and Truth Table
Q
L
H
L
H
A-47.
The J-K flip-flop can also be operated with one
high input and one low input. It then functions in the same
manner as the clocked R-S flip-flop.
A-48.
Figure A-20 includes a truth table showing opera-
tion of the J-K flip-flop. Note that with both inputs high at
the time of clock pulse transition, the final state of the flip-
flop (after clock pulse transition) depends on the state before
the transition. With only one input high, the initial state of
the flip-flop is immaterial.
A-49.
In some cases the J-K flip-flop consists of two sep-
arate flip-flops, with the output of one applied to the input
of the other. Usually, a single flip-flop logic symbol is used
to illustrate this circuit. The clock pulse inverting dot, or the
lack of it, indicates the clock pulse transition that affects
the output flip-flop of the pair.
A-50.
LATCHING FLIP-FLOP. The latching flip-flop
shown in figure A-21 can be recognized by the letter "L" in
A-6
7901A
the symbol. The flip-flop has a clock input and a data
input. Although the logic symbol shows two input-signal
connections to the flip-flop, in reality there is only a single,
physical data input connection to the flip-flop. This single
input separates inside the integrated circuit pack to form
the two inputs shown. After separation, one input is in-
verted (indicated by the inverting dot) before application to
the flip-flop.
~ ---4IH~---f'~-~FF:-I----
Q
~
1----0
t..--_ _
----J
A
C
Q
7900-126
Figure A-21. Latching Flip-Flop Logic Symbol
and Swi tching Waveforms
A-51.
The set-side input is responsive to high signal levels
at A in figure A-22, and the clear input is responsive to low
signal levels at A.
If
there is no inverting dot at the clock in-
put, this response takes place when the clock pulse is high.
While the clock pulse remains high, the outputs follow any
changes in the logic level at A as these changes take place.
When the clock pulse becomes low, the flip-flop retains its
current state, and no longer responds to changes of the input
signal.
7900-127
A
C
Q
--.J
o~
. . . . . . . _ _ --,
Figure A-22. Delay Flip-Flop Logic Symbol
and Switching Waveforms
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