HP 7901A Operating And Service Manual page 121

7901A
~
-------1
C _ _
F_F_~
_ _ _ _
~
A~
B
c
tU
tU
Q
7900-120
Figure A-15. R-S Flip-Flop with Inverted Clock Input,
Logic Symbol, and Switching Waveforms
A-42. In some cases the clocked R-S flip-flop has a set
and clear input at the top and bottom of the logic symbol
(inputs D and E, figure A-16). These inputs are independent
of the clock pulse, and are referred to as the direct set and
direct clear inputs. They function as a result of a high or
low level, rather than a positive- or negative-going transition.
An inverting dot at the direct set or clear input indicates that
a low level is required to set or clear the flip-flop. No dot in-
dicates that a high level is required. The direct set and clear
inputs are also used on other types of flip-flops.
0
I
A
Q
C
Ie
FF
J
B
J
Q
I
7900-121
Figure A-16. Logic Symbol for Clocked R-S Flip-Flop
with Direct Set and Direct Clear Inputs
A-43. TOGGLE FLIP-FLOP. The symbol for the toggle
flip-flop as shown in figure A-17 can be recognized by the
letter "T" in the symbol. This flip-flop has a single input. If
there is no inverting dot at this input, each time the input
signal becomes high, outputs Q and
Q
change state. Since
two inputs are required to produce one complete cycle of
the output, the toggle flip-flop functions as a divide-by-two
element, and is commonly used in groups in counting cir-
cuits, with the output of one flip-flop driving the next. Fig-
ure A-17 shows the switching waveforms for one flip-flop.
Logic Symbology
A
-----II
T --F-F_i-_ _ _ _
~
Q
7900-122
Figure A-17. Toggle Flip-Flop Logic Symbol and
Switching Waveforms
A-44. If a toggle flip-flop symbol has an inverting dot at
the input connection, the flip-flop changes state at the
negative-going transition of the input. The symbol and wave-
forms for this type of flip-flop are shown in figure A-1S.
A
----.t
T - - F F - i -_ _ _ _
~
Q
7900-123
Figure A-1S. Toggle Flip-Flop with Inverted Input, Logic
Symbol, and Switching Waveforms
A-45. J-K FLIP-FLOP. In the J-K flip-flop, simultaneous
high inputs for both set and clear will reverse the existing
state of the flip-flop. This requires some method of storing
two conditions, the previous output state and the new out-
put state, until the clock pulse time. The set and clear inputs
are labeled J and K respectively. In order to provide the nec-
essary output storage the flip-flops are combined in a dual-
rank configuration, together with the necessary gates to
form a single logic element. For simplicity the internal dual-
rank arrangement of the flip-flop is not usually shown. (See
figure A-19.)
A-5