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Section IV
12606B
PART OF
FIRST WORD
SECOND WORD
/~
____________________________
~A~
____________________________
~,/~
______
-JA~
_ _ _ _ _ _
~,
WRITE
BIT NO.
OW
READ
BIT NO.
DR
MC44·8
WRD FF
STR FF
MC104-6
MC84·8
2032-7
Figure 4-6. Write and Read Control, Timing Chart
gate MC15B is disabled by the false input to pin *U of the
card. The input to pin 12 of "nand" gate MC124B on the
data card therefore is true.
4-75.
Returning to "nand" gate MC104A on the com-
mand card, its output, furnished to pins *8 and *17 of the
data card, is true until the WRD FF is set at the end of a
word. Then, while the STR FF remains in the reset
condition, the input to pins *S and *17 of the data card is
false.
4-76.
Coincidence no longer exists for "nand" gate
MC124B on the data card, and its output becomes true.
This true output gates the contents of the input register
into the data shift register. At the same time, the WP FF on
the data card is reset and the Flag FF is set. The Flag FF
sends an SRQ signal to the DMA system indicating that the
second word is required for the input register on the data
card. When the word is supplied, SCM, SCL, IOGE(B), and
100 signals from the DMA system gate the word into the
input register on the data card, and a CLF signal from DMA
resets the Flag FF.
4-77.
Note that prior to the first word stored in each
sector the actions described in the preceding paragraph are
brought about by a true input to pin *U on the data card.
4-10
For subsequent words in the sector, the same actions are
brought about by a false input to pins *S and *17.
4-78.
When the WRD FF is set near the end of the first
word, the positive-going edge of the 17th "not" BC pulse
sets the STR FF. At this time, the word counter is
advanced by binary 1, to indicate that the first word of the
sector has been recorded on the disc.
4-79.
The procedures described for the second word are
repeated for each subsequent word in the sector. After the
64th word of the sector has been written, FF WD5 on the
command card is cleared, setting the EOS FF. Inverter
MC34A on the command card then prevents the enabling of
"nand" gate MC104A, and thereby prevents the Flag FF
from requesting a word from the DMA system.
4-80.
When the WRD FF is set at the end of the 64th
word, "nand" gate MC56C is enabled, and the Run FF is
reset. With the Run FFcleared, the "not" W output
furnished to the disc becomes true, and writing ceases. (See
"not" W signal in figure 4-1.)
4-81.
Operations now await the second "not" SC pulse
of the new sector. This pulse strobes "nand" gates MC54E
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