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12606B
FLIP-FLOP OR REGISTER
Control Bit FF
Data Shift Register
Flag FF
Input Register
Output Register
Read Parity (RP) FF
Track Address Register
Write Parity (WP) FF
Section IV
Table 4-2. Data Card Flip-Flops and Registers
FUNCTION
Set by an STC instruction that uses the I/O select code of the data card. Reset by a CLC
signal generated by the DMA system. Can also be reset by a CLC instruction performed
by the computer, using the I/O select code of the data card. When set, initiates transfer of
data to or from the disc. Remains set during and between disc sectors. When reset,
terminates disc operation at the end of the current disc sector.
When writing, furnishes data to the disc in serial form. When reading, receives data from
the disc in serial form. Flip-flop DO contains the low-order bit before shifting starts
(when writing) or after shifting ends (when reading).
Set when a new word is needed for transfer to the disc (when writing), or set when a new
word has been acquired from the disc (when reading). Initiates action by DMA to furnish
another word (when writing), or to acquire the new disc word (when reading). Cleared by
a CLF signal received from DMA. Can also be cleared by a CLF instruction that uses the
data card I/O select code.
Used only when writing on disc. Receives from DMA each word to be written, and holds
it for loading into the data shift register. Flip-flop IO contains the low-order bit.
Used only when reading from the disc. Receives from the data shift register each word
read from the disc, and holds the word until DMA acquires it. Flip-flop 00 contains the
low-order bit. Contents are changed each time a new word read from the disc is furnished
by the data shift register.
Performs a meaningful function during disc reading only. Reset by the STC instruction
that initiates a read operation. Toggled by each logic zero read from the disc.
If
set at the
end of a 17-bit word, a parity error exists, and the RPE FF on the command card is set.
After the first parity error of a read operation, the RP FF ceases to perform a useful
function.
Contains the address of the track in which writing or reading will take place or is taking
place. Flip-flop TAO contains the low-order bit. The register is loaded by bits 13 thru 7 of
a word transferred from the computer by an OT A/B instruction addressed to the
command card. The register retains its contents after completion of the write or read
operation until another OT A/B instruction loads a new address in the register.
Used to furnish the parity bit when writing on the disc. Set before start of writing each
word, then toggled by each logic 1 sent to the disc. After 16 data bits have been
transferred to the disc, the WP FF is in the condition for furnishing the parity bit. Odd
parity is used.
4-27.
The figures and tables mentioned above should be
referred to as necessary while reading the detailed theory
discussion which follows.
from the unpredictable state of flip-flops during and after
power turn-on. When the computer is not running, pressing
the PRESET switch also generates the CRS signal,
producing the same results as at power turn-on.
4-28.
POWER-ON INITIALIZATION.
4-29.
When power is applied to the computer by the
POWER switch, CRS and POPIO signals are supplied to the
data card for approximately 40 milliseconds. These signals,
consisting of a series of T5 pulses, are inverted on the data
card, and clear the Control Bit FF and Flag FF. The
inverted signal is also forwarded to the command card as
"not" CRF, where it clears the Run FF. When the Run FF
is in the reset condition, the "not" R and "not" W signals
are true, preventing disc reading or writing that could result
4-30.
To further ensure that disc writing does not take
place during the transient conditions of the power turn-on
period, the PON signal from the power fail interrupt card is
applied to the base of transistor Q1 on the command card.
The PON signal is false for about 40 milliseconds during
and after power turn-on. For this period of time it keeps
transistor Q1 cut-off, providing protection against disc
writing. In addition, the PON signal is false during the
power turn-off period, providing protection at that time
also.
4-3
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