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on
the Wideband Amplifier
controls
the
level
(1
MHz
to
1 GHz), and diodes
CR6
and
CR7
are
switched
into
amplifiers
U4
and
U5,
respectively.
These
diodes,
when
switched
on,
reduce
the
low-frequency
gain of U4
and
U5,
keeping
the
ALC
loop stable.
In LO-band mode,
0.01 to
1 MHz, the VCA on the Wideband Amplifier is
set
to
minimum attenuation by
U9,
and
the
output
level is controlled
by
a
VCA in the RF
Synthesizer.
This
VCA
is
controlled
by the 0.01
to
1 AGC
output of
the
Wide band
Amplifier.
Also,
during LO-band
mode,
C30
is
switched
into the detector
circuit.
This increases
the detector time
constant
so
that
the
detector oper-
ates
properly at lower frequencies.
Switching
of
CR6, CR7,
CR9
is controlled
by
com-
parators
on
U6.
17.2.2.2.
6 RF-Switching
In
generate
mode,
the
output
of
the Wideband
Amplifier
is switched
by relay K1
to the
ATTENUA-
TOR OUT/IN
port.
This
signal
then
goes
through the
step attenuator and to the
Wattmeter board where it
is
switched to either the
Antenna
port or the
RF
In/
Out
port.
The
operator can select
the Antenna
or
RF
In/Out port by pulling
out or
pushing
in the variable
RF
Level control
on
the
front panel.
17
.2.2.3
Monitor Mode
In
monitor mode, the MON
+
DSB/GEN input
is
taken high. This
switches a
fixed reference into
sum-
ming amplifier
U8,
which
is set
by R58, resulting in
a
fixed
local-oscillator
drive level out of Q7. This also
energizes
relay
K1,
causing
mixer
U10
to mix
the
mon-
itor input
from
the
ATTENUATOR OUT/IN
port
with
the local-oscillator signal.
A portion
of
the local-oscillator
output
is
sent to the
Duplex
Generator (A17
A3)
through the
L.O. OFFSET
OSC OUT
port.
The
output
of
mixer
U10
is sent
through
the
20-MHz
low-pass filter and
then to the
Receiver
through the
10.7
MHz IF OUT
port.
17.2.2.4
Double
Sideband-Suppressed Carrier
(DSBSC) Mode
For DSBSC
mode,
the
Wideband Amplifier
is
con-
figured as
in
the
monitor
mode,
except
that
modula-
tion
is
applied to
the
DSBSC MOD
input through
the
isolation
network
to
mixer
U10. The resulting
DSBSC
output is coupled
through
relay K1,
to the
ATTEN-
UATOR
OUT/IN
port.
17.2.3
DUPLEX
GENERATOR BOARD
(A17A3)
17.2.3.1
General
The Duplex Generator board provides an RF out-
put whose frequency
is
offset from the Receiver's
cen-
17-3
ter
frequency
by either a fixed 45
MHz
or an adjustable
0 to
10 MHz
in 5-kHz steps. The 45-MHz offset is
obtained
by
mixing the
local-oscillator
signal from the
Wideband Amplifier (L.O. OFFSET), which is offset
by
10.7
MHz from
the
desired Receiver
signal, with a
34.3-MHz
signal generated by a phase-locked-loop
(PLL).
The
0 to 10-MHz adjustable offset is obtained
by mixing
the L.O. OFFSET signal with a 0.7
to
10.7
-MHz
signal.
This
signal
is generated
by
mixing
the
34.3-MHz PLL with
a 35 to 45-MHz PLL.
A
block diagram
of the Duplex Generator
board
is
shown at
the
end of the section
in
Figure
17-10,
a sche-
matic
in Figure
17-11,
and
the
printed wiring
board
assembly
and parts list in Figure 17-12.
17
.2.3.2
Phase-Locked-Loop
(PLL)
Control
The
phase-locked-loops on
the
Duplex
Generator
board
use
a
PLL
integrated circuit (IC).
This
IC
pro-
vides
digital
dividers,
control
functions, the phase
detector,
and
a reference-frequency oscillator. The
reference
oscillator is divided-down
by
the
reference
divider to set the reference frequency of the PLL. This
signal is applied to the phase
detector, where it
is com-
pared
to the output of the divider
chain
(divide-by-N
and
divide-by-A).
The
selection of the
dividers
(ref-
erence,
divide-by-N, and
divide-by-A)
can
be
pro-
grammed by
using
either
hard
wiring or serial
data
lines. The
serial-data-programmable
IC
provides
two
latched
open-drain outputs that can be
used
for exter-
nal
switching.
17.2.3.3
35
to
45-MHz PLL
17.2.3.3.
1
General
The 35 to 45-MHz PLL
consists
of a serial-input
PLL
IC,
a
loop
filter,
a
voltage-controlled
oscillator
(VCO),
an amplifier, and a two-modulus
pre-scaler.
The
reference
oscillator on the PLL IC
(U2)
uses
crystal
Y1 to generate a 10.24-MHz
source. The
ref-
erence divider on U2 divides
this
signal by 2048, pro-
viding a reference frequency of
5
kHz.
The phase
detector then compares this
signal
to the divided-down
VCO output coming from
the
divide-by-N.
The
PLL
uses a divide-by-32/33, two-modulus pre-scaler (U4)
which, in conjunction with
dividers
N and A, divides
the VCO output of
35
to 45 MHz down to
5
kHz.
The
two-output
phase detector
is
connected
to
the loop
fil-
ter.
17.2.3.3.2
Loop Filter
Loop filter
U6 sets
the bandwidth and
stability
of the
loop
and
attenuates the reference-frequency compo-
nents
coming
from
the
phase
detector.
The
3-dB
bandwidth of the
35
to 45-MHz loop is
22Hz.
The
loop
filter incorporates
a lead-lag
network (R29, R30, and
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