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11.1 DESCRIPTION
The
RF Synthesizer
module consists
of
6
sub-mod-
ules:
•
Reference and
Control Board
(A9A1)
•
310
to
440-MHz
Loop Board
(A9A2)
•
Synthesizer
Output
Board
(A9A3)
•
60.5-MHz
Loop
Board
(A9A4)
•
GHz Loop Board (A9A5)
•
640-MHz Loop
Board (A9A6)
plus the
Synthesizer Motherboard
(A9A
7).
The
6
sub-
modules,
which
are
arranged three
per side on
the
Synt
hesizer Motherboard,
are
individually
covered
to
provide EMI
shielding.
A
block
diagram
of the
RF Synthesizer board
is
shown
at
the
end
of
this
section in Figure
11-1,
and
the
locations
of
the 6
sub-modules
are
shown
with
the
assembly and
parts
list
in Figure
11-2.
The
RF
Synthesize
r
module provides
RF
frequen-
cies
from
10kHz
to
1
GHz in
100-Hz
steps
at the
out-
put
port.
The
Synthesizer
module
is
the
primary
signal
source
fo
r
the
system's
generator
output
and
the local-
oscillator
source
for the
system's
receive
function;
it
also
provides
the
10-MHz
TTL
reference
sign al
required
by
the system.
The
reference
signal for
the
RF
Synthesizer
is
provided
by
the
system's
10-MHz
mas-
ter oscillator.
Programming
cont
rol
of the Synthesizer
module
is
via four serial data
busses
with
common clock
and latch
lines.
The system processor provides the
program·
ming
signals.
11.2
THEORY OF OPERATION
The
310
to 440-MHz
Loop board
(A9A2)
provides
synthesized frequencies
between 310
and 440
MHz
in
125-kHz
steps, as
programmed
by
the system
proces-
sor.
That
signal
is
mixed with the
divide-by-two
signal
from
the 500
to 1000-MHz
voltage-controlled
oscilla-
tor
(VCO)
on the GHz Loop
board
(A9A5).
The
result·
ing
difference
frequency
is
compared to
the
60.5-MHz
( ± 125
kHz)
output from the
60.5-MHz Loop
board
(A9A4).
The
output
of the
60.5-MHz
Loop board
is
pro-
grammable
from
60.375
MHz
to 60.625 MHz
in
50-Hz
steps.
The error
signal resulting
from
the
frequency
comparison
drives
the
500
to 1000-MHz
VCO
so
that
the
di
vide-by-two
output
is
equal
to the 310 to 440-
MHz
frequency,
plus
or
minus
the
60.5
±0.25-MHz
frequency.
The
plus
or
minus
condition
is
selected
by
the
processor
during
the
programming
process
and
involves
changing
the sense
of
the
500
to
1000-MHz
loop.
11-1
SECTION
11.
RF SYNTHESIZER MODULE (A9)
The
net result
of
the
process
is
1)
an
output from
the
500 to
1000-MHz
VCO that
covers
the
range
from 500
to 1000-MHz
in
100-Hz
steps,
and
2)
an
output
from
the divide-by-two which
covers
the range
from
250
to
500
MHz
in
50-Hz
steps.
The
50-Hz
increment
is
not
allowed
by
the system
processor,
however,
so
the
oper-
ator
will only
have
100-Hz increments
in this
range.
For output
frequencies
below
250
MHz,
the
output
of
the
500
to 1000-MHz
VCO
is
mixed with a
fixed
640-MHz
signal
from the
640-MHz
Loop board
(A9A6).
The 500
to
1000-MHz output
is
programmed
so
that the
difference
between it and
640
MHz is
equal
to
the
desired
output frequency. A select
switch on
the
Synthesizer
Output board
(A9A3)
chooses
the
appro-
priate signal
path
to
the
output
port,
depending
on
t he
.
desired output
frequency.
The
Reference
and Control
board (A9A1)
provides
the
reference
frequencies
required
by
the other
Syn-
thesizer
boards and the
rest
of
the
system,
and
pro-
vides
data- buffering and
level-shifting fo
r
the
programming
information from
the processor.
The
Synthesizer Motherboard
(A9A
7)
intercon-
nects signals
and
power-supply
voltages
between
the
Synthesizer's
6
s
ub-modules
and
the
System
Mother-
board
(A19).
11 .2.1
REFERENCE AND CONTROL BOARD
(A9A1)
11 .2.1.1 General
T
he Reference and
Control board
provides
the four
necessary
interface
functions
between
the
RF
Synthe-
sizer
and
the
System
Analyzer: 1)
sinewave-to-TTL-
level
translation
of
the
system's
10-MHz
reference,
2)
derivation of
reference
signals
needed
by
other
RF
Synthesizer
sub-modules, 3)
filtering of
the
+33V
input,
and
4)
serial-to-parallel
conversion
of Synthe-
sizer control
data.
Block
diagrams
of
the Reference
and
Control
board
are shown
at the
end of the section in
Figures
11-3a
and
b, a
schematic
in Figure
11
-4,
and
the
printed
wir
ing
board
assembly
and
parts
list
in
Figure
11-5.
11
.2.
1.2
Theory
of
Operation
The
system's 10-MHz
standard
is
converted
from
a
sinewave
to
two
TTL-compatible
signals by Ql, Q2,
Q3,
and
U2.
One
of
t
he TTL
10-MHz signals is
sent
out to
the
Receiver
board
(A8)
and
the
Processor
Interface
board
(All
).
The
other is
divided-down to
provide 1-MHz refe
rences
for
the
310
t.o 440-MHz
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