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steps,
while the
translation
frequency,
f~4·
can
be
pro-
grammed
from
310
to
440 MHz in 0.125-MHz
steps.
ince
a
mixer-phase
detector and a frequency-trans
-
lation
mixer are
used in the
loop,
two
lock-points
exist
for each
combination
of ( 14
and
ft;e
1
•
When
the
loop
is locked in the positive
sense,
f2
=
f
1
4
+
fso,
and when
it
is
locked
in the
negative
sense,
f2
=
f:1
4
-
f6n·
With
the proper
control, therefore,
f.,
may be
pro-
grammed in the
range of 500
to 1000 MHz in
100-H
z
steps,
and
r~
may be programmed
in the
range
of
250
to
500
MHz in 100-Hz
steps.
A block diagram of the GHz Loop board
is
shown
at
the end of the
section in Figure 11
-15, a schematic
in
Figure 11
-16,
and
a printed wiring board
assembly and
parts list
in
Figure 11-17.
11 .2.5 .2 Theory of Operation
11.2.5.2.
1 GHz
Loop
Ul compares
the GHz
loop's
reference signal
(a
phase-shifted version of
fr~
1
)
to
a
frequency
which
equals
the difference between (
14
and f
2 •
During
phase-
lock, the phase detector
generates
an error
signal
which
keeps
the difference frequency phase-locked to fr,
11
•
This
error
signal drives the loop filter
(U2)
which, in
turn,
drives
the
switched
VCOs
(Q1
-Q6).
The
switched
VCOs
then
drive an
RF
amplifier (U3),
the
output of
which
is
split
between the
500 to
1000-MHz
output and
the
divide-by-2
input. The
divide-by-2
(U10)
has
two
outputs.
One
off
these
provides
the
250
to
500
MHz
output.
The other output
drives
an
RF amplifier
(U9),
which,
in
turn,
drives
the
RF port of
the
translation
mixer (U8).
The frequency of the signal
out
of U8
during
phase-
lock
equals
f
1
~,.
This
signal
drives
the
bandpass
ampli-
fie
r
(Q7
and
Q8).
The
phase
of
the inverting
output of
the
bandpass
amplifier
is
compared to
the
phase-
shifted
version
of
fr~•·
The non-inverting
output of
the
bandpass
amplifier
drives
the
L.O.
port
of the
lock-
detect
mixer
(U7).
When
the
loop
is
locked in
the
pos-
itive
sense,
the
lock-detector voltage
is
positive;
how-
ever,
if
the loop
is
locked in the
negative
sense,
the
lock-
detector voltage
is
negative. When
the loop
is
unlocked,
the
lock-detector
voltage
is
zero.
11
.2.
5.2.
2
Acquisition Circuit
Another
important part
of
the
GH
z loop
is
the
acq
uisition
circuit.
This
circuit
helps
the
loop
acq uire
the
lock
point
and ensures that the
loop
locks
in the
desired
sense.
When
the
loop
is
unlocked,
a
current
is
applied
to the
loop
fi
lter,
which
causes
the
VCO
con-
trol
voltage,
and
thus
the
VCO
frequency, to sweep.
When
the loop acquires
a
lock point,
the
lock
detector
wi
ll
indicate
the
sense
of
the
lock
point.
If
the
desired
11
-4
lock
point
has
been
acquired, the
sweep
circuit
will
turn
off,
allowing the
loop to
remain locked.
If, how-
ever,
the
undesired lock
point
has
been acqui red,
the
honker
circuit will turn
on,
force the
VCO
frequency
to its maximum or minimum
point,
and turn off.
As
the
VCO swee ps
back
in the
opposite
direction,
it will
encounter
the
desired lock
point first.
Correct
operation
of
the acquisition
circuit
depends
on proper phasing
of
the
inputs
of
the
lock
detector
(U7)
.
With
the loop in lock and
no applied
loop
stress
(i.e.
the
slew
and
the
bonk
are
turned off a
nd
there is
no frequency
modulation
on the
reference),
the
mag-
nitude of the lock-detector voltage should
be at its
maximum. The
relative
phase
of the
lock
detector's
input
is
adjusted by
a
variable capacitor
(C24) in
the
phase-shift
network.
11 .2.6 640-MHz LOOP BOARD (A9A6)
11 .2.6.1 General
The 640-MHz
Loop board
provides
a
640-MHz
sig-
nal to the
Output
board where it
is used to
mix-down
the
500
to 1000-MHz output
to
between 10
kHz
and
250
MHz.
.
A block
diagram
of
the 640- MHz
Loop
board is
shown at
the
end of the
section in
Figure 11-18,
a
sche-
matic in Figure
11-19,
and the
printed
wiring board
assembly and
parts list
in
Figure
11-20.
11.2.6.2
Theory
of
Operation
The
640-MHz
Loop board provides a
640-MHz sig-
nal to ·the Synthesizer Output board (A9A3) where it
is used
to
mix down
the
500
to
1000-MHz output of the
GHz
Loop board
(A9A5)
to between 10kHz and 250
MHz.
The 10-MHz reference
feeds
a power
splitter formed
by T2
and
R35. One half
of the reference
power
is sent
to
the Reference and
Control
board. The
other half of
the
power drives crystal filter FL1
(if
present), which
removes noise picked up between
the
Frequency-
Standard
Interface
board
(A16)
and the RF Synthe-
sizer module
(A9).
The phase
of
the divided-down
640-
MHz
output from
U1 (divide-by-64)
is
compared to
the
phase of the filtered reference
by the
phase
detector
(U2),
an
analog-multiplier
IC.
Since
U2 does
not
detect the frequency
difference
when
the
loop
is
out of phase-lock,
an
acquisition-assist
circuit (Ql
, RIO,
R1
2,
Rl
3,
and
Cl2) is
required. RIO
offsets
the
phase
detector's
outpu
t
when the loop
is
disabled,
fo rcing
t.he
loop
filter's
output
voltage
low.
When
the 640-MHz output
is
enabled, a beat fre-
q uency
(the
difference
in frequency between the
10-
MHz
reference and the output of U
1) is
detected
at the
outptJt of the
phase
detector
by
Ql. Ql then
applies
th
is
signal to
the
inverting
input
of the
loop-filter
amplifier
(U3),
fo rcing
its output
voltage,
and
hence
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