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The MW-520 PC architecture is illustrated in Figure 5 . It contains the devices
listed below:
Processor
ChipSet
Level 2 cache
SDRAM
Keyboard controller
Display controller
PCMCIA controller
COM1, COM2
COM3, COM4
BIOS Flash
Sound controller
USB
Temperature controller LM77
Touchscreen
Video capturing
The MW-520 computer is based on the Intel EMC-2 Module that includes a
mobile Pentium II or Pentium III CPU chips, and 512KB second level cache.
PCI and ISA buses are used for peripheral device connection.
PCMCIA, VGA, IDE and sound controllers are connected to the PCI bus.
The following devices are connected to the ISA bus:
• the BIOS flash chip
• the keyboard controller
• the super I/O chip (two UARTs, parallel port and floppy disk controller)
• two auxiliary UARTs
• the touchscreen (via UART)
• the processor unit ASIC.
The MW-520 PC architecture complies with Microsoft PC99 requirements.
EMC-2 (Pentium II MMX 333 or Pentium III 500 MHz)
Intel 82371EB (443BX and PIIX4E)
512KB
64 MB (1 × 8M × 64 bit)
128 MB (1 × 16M × 64bit)
256 MB (1 × 256M × 64bit)
Hitachi H647343416
69000 (CHIPS) + 2 MB RAM
PCI1225 (Texas Instruments)
Super I/O National PC87338/PC97338
National PC16550 (2 items)
Intel flash 4 MB - E28F400B5-T60 (Intel)
Solo - 1E (ESS)
(Part of PIIX4E)
Elo™ Resistive Digitizer
Enhanced Video Input Processor (EVIP) SAA7111A
PC Configuration
15
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