Pioneer PRA-BD11 Service Manual page 73

Sdi aes/ebu input board, sdi aes/ebu output board
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5
Pin Descriptions
NUMBER
SYMBOL
1-10
PD9 - PD0
11
PCLKIN
12
V
EE3
13
V
CC3
14
RSV2
15, 19, 21, 27,
NC
28, 30, 32, 37
16
RSV1
17
V
CC2
18
V
EE2
20
LOCK
22
R
SET
23, 26, 29
V
EE
24, 25
SDO, SDO
31
BYPASS
33
RESET
34
V
CC1
35
V
EE1
36, 38
R
+, R
-
VCO
VCO
39, 43
V
EE
40
LBWC
41, 42
LF+, LF-
44
SYNC DIS
5
6
TYPE
I
CMOS or TTL compatible parallel data inputs. PD0 is the LSB and PD9 is the MSB.
I
CMOS or TTL compatible parallel clock input.
-
Most negative power supply connect ion for parallel data and clock inputs.
-
Most positive power supply connect ion for parallel data and clock inputs.
I
Reserved pin. Do not connect.
I
No connect.
I
Reserved pin. Always connect to V
-
Most positive power supply connection for internal logic and digital circuits.
-
Most negative power supply connection for internal logic and digital circuits.
O
TTL level which is high when the internal PLL is locked.
I
External resistor used to set the data output amplitude for SDO and SDO.
-
Most negative power supply connect ion for shielding (not connect ed).
O
Primary, current mode, 75
I
When high, the SMPTE Scrambler and NRZ encoder a re bypasse d.
I
Resets the scrambler when asserted.
-
Most positive power supply connect ion for analog circuits.
-
Most negative power supply connect ion for analog circuits.
I
Differential VCO current setting resistor that sets the VCO frequency.
-
Most negative power supply connect ion (substrate).
I
TTL level loop bandwidth control that adjusts the PLL bandwidth to optimize for lowest
jitter. If the pin is set to ground the loop bandwidth i s BW
loop bandwidth is approximately 3 BW
approximately10 BW
MIN
I
Differential loop filter pins to optimize loop transfer performance at low loop bandwidths
(NC if not used).
I
Sync detect disable. Logic high di sables sync detection. Logic low allows 8 bit operation
by mapping 000-003 to 000 and 3FC-3FF to 3FF .
PRA-BD11
6
7
DESCRIPTION
.
CC
cabl e driving output (inverse and true)
MIN
, if the pin is tied to V
MIN
7
8
. If the pin is left floating, the
the loop bandwidths
CC
8
A
B
C
D
E
F
73

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