Mitsubishi Electric MELSEC-Q Structured Programming Manual page 173

FXCPU Structured Programming Manual
[Device & Common]
Number and name
Interrupt disable and pulse catch
M 8050
(Input interrupt)
I00 disable
M 8051
(Input interrupt)
I10 disable
• When a special M for disabling input interrupt or timer
M 8052
interrupt is ON
(Input interrupt)
Even if an input interrupt or timer interrupt occurs while
I20 disable
acceptance of the corresponding interrupt is disabled, the
M 8053 interrupt program is not executed.
(Input interrupt)
For example, when the interrupt I00
I30 disable
M8050 is ON (to disable the interrupt I00 ), the interrupt
program is not executed even within the interrupt enabled
M 8054
program area.
(Input interrupt)
• When a special M for disabling input interrupt or timer
I40 disable
interrupt is OFF
M 8055
a) When an input interrupt or timer interrupt occurs, it is
(Input interrupt)
I50 disable b) The interrupt program is executed immediately if
M 8056
(Timer interrupt)
I6 disable
M 8057
(Timer interrupt)
I7 disable
M 8058
(Timer interrupt)
I8 disable
M 8059
Counter interrupt Disables interrupts I010 to I060.
disable
M 8056
Pulse catch
X00
M 8057
Pulse catch
X01
Set to ON at the rising edge of the corresponding input signal.
Set to OFF by the RST instruction.
M 8058
Pulse catch
X02
M 8059
Pulse catch
X03
Operation and function
is given while
accepted.
interrupts are enabled by the EI instruction.
If the DI instruction disables interrupts, execution of
the interrupt program is paused until the EI instruction
enables interrupts.
4 Operations of Special Devices (M8000 and later, D8000 and later)
4.1 Special Device List (M8000 and later, D8000 and later)
Applicable model
FX ,
0S
FX
0N
FX
0
- -
- -
They are
provided for the
pulse catch
function as
described below.
Corresponding
FX FX
U 2C
special device
-
-
-
-
-
-
-
-
-
*1
-
-
-
They disable the
interrupt
processing as
described above.
-
-
1
2
3
4
5
6
7
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