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interrupt causes an exit from a low power mode (and therefore activation of the CPU
clocks as well as the peripheral module clocks), the CPU may access the module reg-
isters to determine the interrupt source.
8.2.2.5 Watchdog Timer
The watchdog timer uses a prescaled version of the LOW_REFCLK for its reference
clock. Low-power modes affect this module only if it is considered undesirable for the
watchdog to time out (causing the MMC2001 to reset) when the chip is in stop or
doze mode. In stop and doze mode, if so programmed, the watchdog ceases opera-
tion and freezes at the current value. When exiting these modes, the watchdog
resumes operation from the freeze value. It is the responsibility of software to avoid
erroneous operation.
8.2.2.6 Interval Timer
The interval timer uses a prescaled version of the LOW_REFCLK for its reference
clock. In stop and doze mode, if so programmed, the PIT ceases operation, and
freezes at the current value. When exiting these modes, the PIT resumes operation
from the freeze value. It is the responsibility of software to avoid erroneous operation.
8.2.2.7 Time-of-Day Timer
The time-of-day timer module uses a prescaled version of the LOW_REFCLK for its
reference clock and does not stop in any of the low power modes.
8.2.2.8 Keypad Port
The keypad port module uses the CPU_CLK for its internal operation only for CPU
accesses, thus the module is not affected by the low power modes and is capable of
waking up the CPU from all low power modes unless it is explicitly disabled. A pres-
caled version of LOW_REFCLK is used for the debounce logic and continues to run
in all modes.
8.2.2.9 Peripheral State During Low-Power Modes Summary
The functionality of each of the peripherals and CPU core during the various low
power modes is summarized in Table 8-2. The status of each peripheral during a
given mode refers to the condition the peripheral automatically assumes when the
particular instruction (wait, doze, or stop) is executed. (It is possible to disable an indi-
vidual peripheral by programming its dedicated control bits.) The wake-up capability
field refers to the ability of an interrupt from that peripheral to force the CPU into run
mode.
8.2.2.10 Standby Mode Summary
The functionality of each of the peripherals and CPU core during the standby mode is
summarized in Table 8-2. Standby mode is selected when the LVRSTIN pin is
asserted. All modules except for the low-power oscillator (OSC) and the time-of-day
timer (TOD) are held in reset in this mode. The TOD continues to run.
MOTOROLA
8-6
Freescale Semiconductor, Inc.
CLOCK MODULE AND LOW-POWER MODES
For More Information On This Product,
Go to: www.freescale.com
MMC2001
REFERENCE MANUAL
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