Spi Manual/Interval Mode Timing (Pha = 0; Spi Manual/Interval Mode Timing (Pha = 1 - Motorola M-CORE MMC2001 Series Reference Manual

SPI_EN
(Output,
SNS=1)
SPI_EN
(Output, SNS=0)
52
SCLK
(Output, POL=0)
SCLK
(Output, POL=1)
SPI_MOSI
TBD
(Output)
56
SPI_MISO
(Input)
NOTE: The sequential transfer delay is determined by the settings in the SPI interval control register.
Figure A-8 SPI Manual/Interval Mode Timing (PHA = 0)
SPI_EN
(Output,
SNS=1)
SPI_EN
(Output, SNS=0)
52
54
SCLK
(Output, POL=0)
SCLK
(Output, POL=1)
55
SPI_MOSI
(Output)
TBD
SPI_MISO
(Input)
NOTE: The sequential transfer delay is determined by the settings in the SPI interval control register.
Figure A-9 SPI Manual/Interval Mode Timing (PHA = 1)
MOTOROLA
A-8
Freescale Semiconductor, Inc.
51
54 55
55
54
60
MSB OUT DATA
57
MSB IN
DATA
51
55
54
60
MSB OUT DATA
56 57
MSB IN
DATA
ELECTRICAL CHARACTERISTICS
For More Information On This Product,
Go to: www.freescale.com
62
63
62 63
61
LSB OUT
LSB IN
53
62 63
62
63
61
59
LSB OUT
LSB IN
NOTE
64
53
61
TBD MSB OUT
PD*
MSB IN
NOTE
64
MSB OUT
TBD
PD* MSB IN
MMC2001
REFERENCE MANUAL