Table of Contents
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2.1
M•CORE Overview .......................................................................................... 2-1
2.2
Features ........................................................................................................... 2-2
2.3
Microarchitecture Summary ............................................................................. 2-2
2.4
Programming Model......................................................................................... 2-3
2.5
Data Format Summary..................................................................................... 2-5
2.6
Operand Addressing Capabilities..................................................................... 2-6
2.7
Instruction Set Overview .................................................................................. 2-6
2.8
M•CORE Bus Interface .................................................................................... 2-8
2.8.1
Bus Characteristics ....................................................................................... 2-8
2.8.2
Bus Signals ................................................................................................... 2-9
2.8.3
Signal Descriptions...................................................................................... 2-10
2.8.4
Bus Operation ............................................................................................. 2-11
2.8.5
Processor Instruction/Data Transfers .......................................................... 2-13
2.8.6
Bus Exception Cycles.................................................................................. 2-14
3.1
Overview .......................................................................................................... 3-1
3.2
Peripheral Module Address Allocation ............................................................. 3-1
3.3
Peripheral Module Interface Operation ............................................................ 3-2
3.4
Peripheral Module Address Assignment .......................................................... 3-2
4.1
Overview .......................................................................................................... 4-1
4.2
Signal Index ..................................................................................................... 4-2
4.3
Bus Signals ...................................................................................................... 4-4
4.3.1
Address Bus (ADDR[19:0]) ........................................................................... 4-4
4.3.2
Data Bus (DATA[15:0]).................................................................................. 4-4
4.3.3
Output Enable (OE)....................................................................................... 4-4
4.3.4
Read/Write Enable (R/W) .............................................................................. 4-4
4.3.5
Enable Byte 1 (EB1)...................................................................................... 4-4
4.3.6
Enable Byte 0 (EB0)...................................................................................... 4-4
4.3.7
Chip Selects (CS3, CS[2:0]).......................................................................... 4-4
4.3.8
Internal ROM Disable (MOD) ........................................................................ 4-4
4.4
Exception Control Signals ................................................................................ 4-4
4.4.1
Reset (RSTIN)............................................................................................... 4-4
4.4.2
Low Voltage Reset (LVRSTIN) ...................................................................... 4-5
4.4.3
Reset Out (RSTOUT) .................................................................................... 4-5
MMC2001
REFERENCE MANUAL
Freescale Semiconductor, Inc.
TABLE OF CONTENTS
Title
SECTION 1
INTRODUCTION
SECTION 2
SECTION 3
SECTION 4
For More Information On This Product,
Go to: www.freescale.com
Page
MOTOROLA
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