Chapter 4 Functional Description; Peripheral Component Interconnect (Pci) Local Bus Interface; Compactpci Bus Interface - Motorola CompactPCI CPN5365 Installation And Use Manual

Functional Description
Pentium III Processor
4
Peripheral Component Interconnect (PCI)
Local Bus Interface

CompactPCI Bus Interface

4-2
The CPN5365 supports a low power Intel Mobile Pentium III processor
that is based on 0.18 micron process. The processor executes Intel MMX
technology instruction for enhanced media and communication
performance. It includes an integrated on-die L1 4-way associative L1
cache with 16KB instruction and 16KB write-back data cache, and an on-
die 256KB, ECC protected cache data array, 8-way set associative L2
cache that operates at full core speed. For further information, refer to
Appendix C, Related Documentation
processor data sheet.
The PCI local bus is a high-performance, 32-bit bus with multiplexed
address and data lines. Use it as an interconnect mechanism between
highly-integrated peripheral controller components, peripheral add-in
boards and processor/memory systems.
The CPN5365 supports a 32-bit local PCI bus interface. On-board devices
connect directly to the local PCI bus.
The CPN5365 supports a single 64-bit CompactPCI bus interface. You can
insert the physical connector into a 64-bit High Availability CompactPCI
backplane and make connection to off-card CompactPCI peripherals
through the Intel 21555 PCI-PCI bridge.
Unlike a transparent PCI-to-PCI bridge, the Intel 21555 is designed to
bridge two processor domains. The system CompactPCI bus is connected
to the primary bus side of the bridge, which is also referred to as the host
domain or the host processor side. The secondary bus interfaces to the
local PCI bus, referred to as the local domain or local processor side. The
bridge chip supports independent primary and secondary address spaces
for the Intel Mobile Pentium III
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