Epson S1C31D50 Technical Manual page 418

APPENDIX A LIST OF PERIPHERAL CIRCUIT CONTROL REGISTERS
Address Register name
0x0020 DMACENCLR
102c (DMAC Enable Clear
Register)
0x0020 DMACPASET
1030
(DMAC Primary-Alter-
nate Set Register)
0x0020 DMACPACLR
1034 (DMAC Primary-Alter-
nate Clear Register)
0x0020 DMACPRSET
1038 (DMAC Priority Set
Register)
0x0020 DMACPRCLR
103c (DMAC Priority Clear
Register)
0x0020 DMACERRIF
104c
(DMAC Error Interrupt
Flag Register)
0x0020 DMACENDIF
2000 (DMAC Transfer
Completion Interrupt
Flag Register)
0x0020 DMACENDIESET
2008 (DMAC Transfer
Completion Interrupt
Enable Set Register)
0x0020 DMACENDIECLR
200c (DMAC Transfer
Completion Interrupt
Enable Clear Register)
0x0020 DMACERRIESET
2010
(DMAC Error Interrupt
Enable Set Register)
0x0020 DMACERRIECLR
2014 (DMAC Error Interrupt
Enable Clear Register)
AP-A-54
Bit Bit name
31–24 –
23–16 –
15–8 –
7–4 –
3–0 ENCLR[3:0]
31–24 –
23–16 –
15–8 –
7–4 –
3–0 PASET[3:0]
31–24 –
23–16 –
15–8 –
7–4 –
3–0 PACLR[3:0]
31–24 –
23–16 –
15–8 –
7–4 –
3–0 PRSET[3:0]
31–24 –
23–16 –
15–8 –
7–4 –
3–0 PRCLR[3:0]
31–24 –
23–16 –
15–8 –
7–1 –
0 ERRIF
31–24 –
23–16 –
15–8 –
7–4 –
3–0 ENDIF[3:0]
31–24 –
23–16 –
15–8 –
7–4 –
3–0 ENDIESET[3:0]
31–24 –
23–16 –
15–8 –
7–4 –
3–0 ENDIECLR[3:0]
31–24 –
23–16 –
15–8 –
7–1 –
0 ERRIESET
31–24 –
23–16 –
15–8 –
7–1 –
0 ERRIECLR
Seiko Epson Corporation
Initial Reset R/W
– – R
– – R
– – R
– – R
– – W
0x00 – R
0x00 – R
0x00 – R
0x0 – R
0x0 H0 R/W
– – R
– – R
– – R
– – R
– – W
0x00 – R
0x00 – R
0x00 – R
0x0 – R
0x0 H0 R/W
– – R
– – R
– – R
– – R
– – W
0x00 – R
0x00 – R
0x00 – R
0x00 – R
0 H0 R/W
0x00 – R
0x00 – R
0x00 – R
0x0 – R
0x0 H0 R/W
0x00 – R
0x00 – R
0x00 – R
0x0 – R
0x0 H0 R/W
– – R
– – R
– – R
– – R
– – W
0x00 – R
0x00 – R
0x00 – R
0x00 – R
0 H0 R/W
0x00 – R
0x00 – R
0x00 – R
0x00 – R
– – W
S1C31D50/D51 TECHNICAL MANUAL
Remarks
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Cleared by writing 1.
Cleared by writing 1.
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(Rev. 2.00)