13 UART (UART3)
UART3 Ch.n Transmit Data Register
Register name
Bit
UART3_nTXD
15–8 –
7–0 TXD[7:0]
Bits 15–8 Reserved
Bits 7–0
TXD[7:0]
Data can be written to the transmit data buffer through these bits. Make sure the UART3_nINTF.
TBEIF bit is set to 1 before writing data.
UART3 Ch.n Receive Data Register
Register name
Bit
UART3_nRXD
15–8 –
7–0 RXD[7:0]
Bits 15–8 Reserved
Bits 7–0
RXD[7:0]
The receive data buffer can be read through these bits. The receive data buffer consists of a 2-byte
FIFO, and older received data is read first.
UART3 Ch.n Status and Interrupt Flag Register
Register name
Bit
UART3_nINTF
15–10 –
9
8
7
6
5
4
3
2
1
0
Bits 15–10 Reserved
Bit 9
RBSY
This bit indicates the receiving status. (See Figure 13.5.3.1.)
1 (R):
During receiving
0 (R):
Idle
Bit 8
TBSY
This bit indicates the sending status. (See Figure 13.5.2.1.)
1 (R):
During sending
0 (R):
Idle
Bit 7
Reserved
13-14
Bit name
Initial
0x00
0x00
Bit name
Initial
0x00
0x00
Bit name
Initial
0x00
RBSY
0
TBSY
0
–
0
TENDIF
0
FEIF
0
PEIF
0
OEIF
0
RB2FIF
0
RB1FIF
0
TBEIF
1
Seiko Epson Corporation
Reset
R/W
–
R
–
H0
R/W
Reset
R/W
–
R
–
H0
R
Reset
R/W
–
R
–
H0/S0
R
H0/S0
R
–
R
H0/S0
R/W
Cleared by writing 1.
H0/S0
R/W
Cleared by writing 1 or reading the
UART3_nRXD register.
H0/S0
R/W
H0/S0
R/W
Cleared by writing 1.
H0/S0
R
Cleared by reading the UART3_nRXD
register.
H0/S0
R
H0/S0
R
Cleared by writing to the UART3_
nTXD register.
S1C31D50/D51 TECHNICAL MANUAL
Remarks
Remarks
Remarks
(Rev. 2.00)