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2 POWER SUPPLY, RESET, AND CLOCKS
(1) When the CLGSCLK.WUPMD bit = 0
SYSCLK
(CPU operating clock)
CLGSCLK.CLKSRC[1:0] = 0x1 (OSC1)
CLGSCLK.WUPSRC[1:0] = 0x1 (OSC1)
(2) When the CLGSCLK.WUPMD bit = 1 and the CLGSCLK.WUPSRC[1:0] bits = 0x0
SYSCLK
(CPU operating clock)
CLGSCLK.CLKSRC[1:0] = 0x1 (OSC1)
CLGSCLK.WUPSRC[1:0] = 0x0 (IOSC)
Clock external output (FOUT)
The FOUT pin can output the clock generated by a clock source or its divided clock to outside the IC. This al-
lows monitoring the oscillation frequency of the oscillator circuit or supplying an operating clock to external
ICs. Follow the procedure shown below to start clock external output.
1. Assign the FOUT function to the port.
2. Configure the following CLGFOUT register bits:
- CLGFOUT.FOUTSRC[1:0] bits
- CLGFOUT.FOUTDIV[2:0] bits
- Set the CLGFOUT.FOUTEN bit to 1. (Enable clock external output)
OSC3 oscillation auto-trimming function
The auto-trimming function adjusts the OSC3CLK clock frequency by trimming the clock with reference to
the high precision OSC1CLK clock generated by the OSC1 oscillator circuit (crystal oscillator). However, this
function is effective only when 16 MHz (CLGOSC3.OSC3FQ[1:0] bits = 0x3) has been selected to the OSC3
oscillation frequency.
Follow the procedure shown below to enable the auto-trimming function.
1. After enabling the OSC1 oscillation, check if the stabilized clock is supplied (CLGINTF.OSC1STAIF bit = 1).
2. After enabling the OSC3 oscillation, check if the stabilized clock is supplied (CLGINTF.OSC3STAIF bit = 1).
3. Write 0x0096 to the SYSPROT.PROT[15:0] bits. (Remove system protection)
4. Configure the following CLGINTF register bits:
- Write 1 to the CLGINTF.OSC3TEDIF bit.
- Write 1 to the CLGINTF.OSC3TERIF bit.
5. Configure the following CLGINTF register bits:
- Set the CLGINTE.OSC3TEDIE bit to 1.
- Set the CLGINTE.OSC3TERIE bit to 1.
6. Write 1 to the CLGOSC3.OSC3STM bit.
7. Write a value other than 0x0096 to the SYSPROT.PROT[15:0] bits. (Set system protection)
8. The trimmed OSC3CLK can be used if the CLGINTF.OSC3TEDIF bit = 1 after an interrupt occurs. If the
CLGINTF.OSC3TERIF bit = 1, an error has occurred during the auto-trimming operation (the clock has not
been adjusted).
After the trimming operation has completed, the CLGOSC3.OSC3STM bit automatically reverts to 0. Although
the trimming time depends on the temperature, an average of several 10 ms is required.
2-12
SLEEP mode
OSC1CLK
(CPU stop, CLK stop)
Executing the WFI/WFE instruction
(SLEEPDEEP bit = 1)
SLEEP mode
OSC1CLK
(CPU stop, CLK stop)
Executing the WFI/WFE instruction
(SLEEPDEEP bit = 1)
Figure 2.3.4.4 Clock Control Example at SLEEP Cancelation
(Refer to the "I/O Ports" chapter.)
(Select clock source)
(Set clock division ratio)
Seiko Epson Corporation
Oscillation stabilization waiting time
OSC1CLK
(Unstable)
Interrupt
(Wake-up)
∗ Starting up with the same clock as one
that used before SLEEP mode was entered.
IOSCCLK
(Unstable)
Interrupt
(Wake-up)
CLGSCLK.CLKSRC[1:0] = 0x0 (IOSC)
CLGSCLK.WUPSRC[1:0] = 0x0 (IOSC)
∗ Switching to IOSC that features fast
initiation allows high-speed processing.
(Clear interrupt flag)
(Clear interrupt flag)
(Enable interrupt)
(Enable interrupt)
(Enable OSC3 oscillation auto-trimming)
S1C31D50/D51 TECHNICAL MANUAL
OSC1CLK
IOSCCLK
(Rev. 2.00)
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