0X0020 0720-0X0020 0732 Ir Remote Controller (Remc3) - Epson S1C31D50 Technical Manual

Address Register name
0x0020 I2C_2TBEDMAEN
06f4 (I2C Ch.2 Transmit
Buffer Empty DMA
Request Enable
Register)
0x0020 I2C_2RBFDMAEN
06f6
(I2C Ch.2 Receive
Buffer Full DMA
Request Enable
Register)
0x0020 0720–0x0020 0732
Address Register name
0x0020 REMC3CLK
0720
(REMC3 Clock Con-
trol Register)
0x0020 REMC3DBCTL
0722 (REMC3 Data Bit
Counter Control
Register)
0x0020 REMC3DBCNT
0724
(REMC3 Data Bit
Counter Register)
0x0020 REMC3APLEN
0726 (REMC3 Data Bit
Active Pulse Length
Register)
0x0020 REMC3DBLEN
0728
(REMC3 Data Bit
Length Register)
0x0020 REMC3INTF
072a (REMC3 Status
and Interrupt Flag
Register)
0x0020 REMC3INTE
072c (REMC3 Interrupt
Enable Register)
0x0020 REMC3CARR
0730
(REMC3 Carrier
Waveform Register)
0x0020 REMC3CCTL
0732
(REMC3 Carrier
Modulation Control
Register)
S1C31D50/D51 TECHNICAL MANUAL
(Rev. 2.00)
APPENDIX A LIST OF PERIPHERAL CIRCUIT CONTROL REGISTERS
Bit Bit name
15–8 –
7–4 –
3–0 TBEDMAEN[3:0]
15–8 –
7–4 –
3–0 RBFDMAEN[3:0]
Bit Bit name
15–9 –
8 DBRUN
7–4 CLKDIV[3:0]
3–2 –
1–0 CLKSRC[1:0]
15–10 –
9 PRESET
8 PRUN
7–5 –
4 REMOINV
3 BUFEN
2 TRMD
1 REMCRST
0 MODEN
15–0 DBCNT[15:0]
15–0 APLEN[15:0]
15–0 DBLEN[15:0]
15–11 –
10 DBCNTRUN
9 DBLENBSY
8 APLENBSY
7–2 –
1 DBIF
0 APIF
15–8 –
7–2 –
1 DBIE
0 APIE
15–8 CRDTY[7:0]
7–0 CRPER[7:0]
15–9 –
8 OUTINVEN
7–1 –
0 CARREN
Seiko Epson Corporation
Initial Reset R/W
0x00 – R
0x0 – R
0x0 H0 R/W
0x00 – R
0x0 – R
0x0 H0 R/W
IR Remote Controller (REMC3)
Initial Reset R/W
0x00 – R
0 H0 R/W
0x0 H0 R/W
0x0 – R
0x0 H0 R/W
0x00 – R
0 H0/S0 R/W
0 H0/S0 R/W
0x0 – R
0 H0 R/W
0 H0 R/W
0 H0 R/W
0 H0 W
0 H0 R/W
0x0000 H0/S0 R
0x0000 H0 R/W
0x0000 H0 R/W
0x00 – R
0 H0/S0 R
0 H0 R
0 H0 R
0x00 – R
0 H0/S0 R/W
0 H0/S0 R/W
0x00 – R
0x00 – R
0 H0 R/W
0 H0 R/W
0x00 H0 R/W
0x00 H0 R/W
0x00 – R
0 H0 R/W
0x00 – R
0 H0 R/W
Remarks
–
–
Remarks
–
–
Cleared by writing 1 to the
REMC3DBCTL.REMCRST
bit.
–
Cleared by writing 1 to the
REMC3DBCTL.REMCRST
bit.
Writing enabled when
REMC3DBCTL.MODEN bit
= 1.
Writing enabled when
REMC3DBCTL.MODEN bit
= 1.
–
Cleared by writing 1 to the
REMC3DBCTL.REMCRST
bit.
Effective when the
REMC3DBCTL.BUFEN bit =
1.
–
Cleared by writing 1 to this
bit or the REMC3DBCTL.
REMCRST bit.
–
–
–
AP-A-49