Sony CXD2701Q Data Book page 136

SONY,
CX01
IGOAP.'AO
Delay
I/O
delay
mode
By
fixing
input pin
DYSL
to
+5V,
delay I/O turns
to
delay
mode.
In this
case, delay
I/O
composes
the
delay space by
utilizing
the
64K
nit
x
1
DRAM
connected
to
the
exterior,
64K
x
1=1024 sample
x (32
bit
+ 32
bit)
That
is,
32
bit
data
1
to
1024 sample stereo delay
is
performed. This stereo delay
sample
volume
is
set through
the
microcomputer
interface
R mode
(R9
to
R0).
R9 R8
R7
R6 R5
R4
R3
R2 Rl
R0
No.
of
delay
sample
r
L L L L L
L
L L L
L
1
H H H
H
H
:i
:-i
H H
H
2
H
H
II
It
H
H
n H
H
L
3
it
II
M
H
H
H H H L U
4
I
L L
L
L
L L
L
L
H
H
10
2
2
1.
L L L
L L
L L
H
L
10
2
3
L
L
L
L
L L
L
L
L H
10
2 4
Outline
of
the timing
system
is
as
follows.
LRCK
XWSO(WE)
DO
register
Dl register
J~
u
*
1
*
u
CH2(n-1) X
CHIInl
X
CH2(nl X
CHUn-il
X
.
CH2(n-1-r]J(
CH1ln-r)
X
CH2ln-r)
X
CH1!rv+1-r)
X'
*
Calculating operations
*•
*DO
register indicates
data entered
in
the
last
part of that
space.
That
is
if
data
CH1
(n) is
written in
DO
register of
1
LRCK
(calculating operations)
first
half,
then
data
CHI
(n-r)
can be
read from Dl
register.
If
data
CH2
(n)
is
written
in
DO
register at
the
second
half,
then data
CH2
(n-r)
can be read from
Dl register.
Connection
to
the external
DRAM
is
as seen on
the
fig
at right
fixed.
Fix
addresses over
A8
to
+5V
or
GND.
Moreover,
for
addresses
that
move
frequently the
order
is;
Column AO
to
A4,
Row
A0
to
A7,
and column
AS
to
A7.
There are 2 kinds
of
data
bit
length
for
delay
32
bit
and 30
bit.
Timing system
differs
according
to
type,
A7-A0
XRAS
XCA5
XWSO
DIO
DYSL
fixed
+5V
aoiiawp
r
A8
A7-AO
RAS
CAS
WE
01
DO
DR«1
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