Sony CXD2701Q Data Book page 114

SONY*
CXD1160AP/AQ
No
Symbol
I/O
Description
19
A7
External
DRAM
address oitput
A7
20
XCLR
I
Test
pin.
Normally
fix
to
+iV
21
Vdd
-
+5V Supply
pin
22
A1 External
DRAM
address output
A1
23
A2
External
DRAM
address
output
A2
24 A0
External
DRAM
address output
AO
25
XRAS
External
DRAM
low
address strobe output
pin
26
xwso
When DYSL
is at
'L'.
turns
to serial
data output
pin,
and
operates
according
to
the various
serial I/O
modes.
When DYSL
is at
'H'
turns
into
the write
enable
output
pin of the external
DRAM.
27 DIO
I/O
Turns
to
serial
data input pin
when
DYSL
is
at
'L"
and
takes
in
according
to
the various
serial
I/O
modes. Turns
into
external
DRAM
data I/O pin
when DYSL
is at 'H'
to
assume
a
common
bus with
DRAM
data input Din
and data output Dout.
28
XCAS
External
DRAM
column address strobe output
pin
Pin Configuration
and
Pin
Description
(CXD116QAQ)
Pin Configuration
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65:
80 c
(TOP
VIEW)
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24
25
Pin Description
No.
Symbol
I/O
Description
1-3
N.C
4
TST
1
Test
pin.
Normally
fixed
to
GNO.
5-8
N.C
9
Vss
- GND
pin
10-15
N.C
16
MCK1
I
Master
dock
input
1
.
Master
clock
ACK
inside the IC
is
half this
frequency.
To
input the
master clock through
MCK
1 fix
MCK2
to
+5V.
-
no