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SONY,
CXD1160AP/AQ
Delay
I/O serial
mode
By
fixing
input
pin
OYSL
to
GND
delay
I/O
turns
to serial
mode.
In
this
case
delay
I/O
operates as
serial I/O.
That
is
the timing
system
is
regulated
by
LRCK
and
BCK
and
the
format
by SI02, SI01 and SIOO.
Also,
serial
input
data
is
input
and
output
Irom DIO/
SI
pin,
and
serial
output data,
from
XWSO
pin.
Delay
I/O register
is
monoral.
When
it
is
input'output
twice
to
1LRCK,
stereo operation
Is
executed.
An
outline of
delay
I/O
input/output
system
timing
is
as
follows.
DIOISH
1
eh
2
data
-X
ch
1
data
)
(
XWSO(SO)
r
)
t-
ch2data "1*
ch
1
data
'
i
(
LRCK 1
p
1
1
*-
i
—
Calculating operation -
Dl
register
\<£
^
(
DO
register
>
w'
^'
The
detailed timing
of
delay
I/O input/output register
is
as
follows.
LRCK
P
I
bck t
_i
—
l
[
i
r (
i
i
l
i
i
r
DIO/
XWSO
"
E
2SB
r
LSB
K
))
1
?SB
1
I
53
<
(Sll
ISO)
^
—
•.
Section
where
gate
latch
is
-«
—
-
.
1
applied
to
Dl register,
DO
register
value
is
latched
to
shift
register.
Dl
register
value contained
in
the
first
half of
1LRCK
calculating
operations
is
the
serial
input
data
of
the
second
half
of
the
preceding
LRCK,
Dl register
value
is
similarly
the
serial
input
data
of
LRCK
first
half.
Also,
the value entered
to
DO
register
in
the
first
half
becomes
the
serial
output
data
of
the
same
LRCK
latter half
in
the
1
LRCK
calculating
operations.
The
value entered
in
DO
register
during
the
second
half
becomes
the
serial
output
data
in
the
first
half of
the following
LRCK.
Dl
register
read
prohibit
cycle
around
LRCK
falling
edge and
DO
register write prohibit
cycle
change
in
relation to
LRCK,
BCK
and
the
original oscillation.
D
I
or
DO
registers
handling
around
this
area should
be
performed
after
due
confirmation.
During delay
I/O
serial
mode,
turn
open
the
external
DRAM
pins
for
delay
mode,
that
is
XRAS,
XCAS
and
A7
to
AO, 10
in all.
I
131
-
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