Sony DVP-NW50 Service Manual page 49

• IC Pin Function Description
MAIN BOARD U1 EP9301-CQZ (CIRRUS) (SYSTEM CONTROLLER)
Pin No. Pin Name
1 CS7
2 CS6
3 CS3
4 CS2
5 CS1
6 AD25
7 VDD_RING
8 GND_RING
9 AD24
10 SDCLK
11 AD23
12 VDD_CORE
13 GND_CORE
14 SDWEN
15 SDCSN3
16 SDCSN2
17 SDCSN1
18 SDCSN0
19 VDD_RING
20 GND_RING
21 RASN
22 CASN
23 DQMN1
24 DQMN0
25 AD22
26 AD21
27 VDD_RING
28 GND_RING
29 DA15
30 AD7
31 DA14
32 AD6
33 DA13
34 VDD_CORE
35 GND_CORE
36 AD5
37 DA12
38 AD4
39 DA11
40 AD3
41 VDD_RING
42 GND_RING
43 DA10
44 AD2
45 DA9
46 AD1
47 DA8
I/O
O Chip select signal output (not used)
O FLASH MEMORY chip select signal output
O Chip select signal output (not used)
O Chip select signal output (not used)
O Chip select signal output (not used)
O Shared address bus out (not used)
— Power supply +3.3V
— Ground terminal
O Shared address bus out (not used)
O SDRAM clock out
O Shared address bus out
— Power supply +1.8V
— Ground terminal
O SDRAM write enable out
O SDRAM chip selects out
O SDRAM chip selects out (not used)
O SDRAM chip selects out (not used)
O SDRAM chip selects out (not used)
— Power supply +3.3V
— Ground terminal
O SDRAM RAS out
O SDRAM CAS out
O Shared data mask out
O Shared data mask out
O Shared address bus out
O Shared address bus out
— Power supply +3.3V
— Ground terminal
I/O Shared data bus in/out
O Shared address bus out
I/O Shared data bus in/out
O Shared address bus out
I/O Shared data bus in/out
— Power supply +1.8V
— Ground terminal
O Shared address bus out
I/O Shared data bus in/out
O Shared address bus out
I/O Shared data bus in/out
O Shared address bus out
— Power supply +3.3V
— Ground terminal
I/O Shared data bus in/out
O Shared address bus out
I/O Shared data bus in/out
O Shared address bus out
I/O Shared data bus in/out
Description
DVP-NW50
49