Sony DVP-NW50 Service Manual page 48

DVP-NW50
– DVD AMP Board –
U202 AT25F1024AN
STATUS
REGISTER
MODE
CS 1
DECODE
LOGIC
OUTPUT
SO 2
BUFFER
WP 3
GND 4
U402, U403, U501, U502, U601, U602 TAS5121DKDR
DVDD DREG
GND 1
PWM
PWM BP 2
RECEIVER
GND 3
DGND
RESET 4
DREG RTN 5
DIGITAL
DREG
REGULATOR
Internally
GVDD 6
connected
to GVDD
M3 7
DREG 8
DGND 9
M1 10
DREG
M2 11 PROTECTION
LOGIC
DVDD 12
OT
SD 13
&
UVP
DGND 14
OTW 15
DVDD DREG
GND 16
PWM
PWM AP 17
RECEIVER
GND 18
DGND
48
ADDRESS
MEMORY ARRAY
DECODER
CLOCK
GENERATOR
DATA
REGISTER
GVDD
DREG OCH
GATE
DRIVE
TIMING
CONTROL
&
PROTECTION
GATE
DRIVE
OCL
OCL
GATE
DRIVE
TIMING
CONTROL
&
PROTECTION
GATE
DRIVE
DREG OCH
GVDD
8 VCC
7 HOLD
6 SCK
5 SI
36 GVDD B
35 GVDD B
34 GND
33 BST B
32 PVDD B
31 PVDD B
30 OUT B
29 OUT B
28 GND
27 GND
26 OUT A
25 OUT A
24 PVDD A
23 PVDD A
22 BST A
21 GND
20 GVDD A
19 GVDD A