Block Diagram - Main (3) Section - Sony DVP-NW50 Service Manual

DVP-NW50
6-4. BLOCK DIAGRAM — MAIN (3) SECTION —
U15 U22
OSC OSC
2 4 2 4
Y1
36.768KHz
X1
14.7456MHz
J3
JTAG PART
DVP-NW50
U1 (3/3)
SYSTEM CONTROLLER
DQM0 24
DQM1 23
SD WEN 14
CASN 22
RASN 21
SDCLKEN 208
SDCLK 10
SDCSN3 15
48,46
44,40
38,36
32,30
73,71
AD0
69,65
I
63,61
AD23
59,55
195,196
205,206
207,26
137 RTCXTALI
25,11
74,72
70,68
64,62
DA0
60,56
I
47,45
DA15
43,39
37,33
31,29
118 XTALI
RVDD
CS6 2
155 TRSTN
RSTON 124
77 TCK
RDN
193
78 TDI
WRN 194
79 TDO
80 TMS
15 LDQM
39 UDQM
16 WE
17 CAS
18 RAS
U3
37 CKE
SDRAM
38 CK
19 CS
20,21 2,4,5,7,8,10,11
22-26 13,42,44,45,47
29-36 48,50,51,53
ADDRES BUS
DATA BUS
28 - 17 33,35,38,40,44
13 - 10 46,49,51,34,36
8 - 3, 1, 30 39,41,45,47,50,52
14 CE0
16 RST
U4
EP$RD
54 OE
FLASH MEMORY
EP$WR
55 WE
26 26
U13 3.3VDC
CVDD (1.8V)
REG
D15
RVDD (3.3V)
L11
CD$VCC3V
D14
VCC5V U14 14VDC
CD$VCC5V
+5V REG
12T05VCC
U20
VCC9V
+9V REG
AMP
E
SECTION
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