Mapi-400+100 Interface; Mapi0 Interface Assignment; Assignment Of J1/P1 (Co600) Connector - Motorola EVB555 Quick Reference

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A.1 MAPI-400+100 Interface
A.1.1 MAPI0 Interface Assignment
A.1.1.1 Assignment of J1/P1 (CO600) connector:
Pin
MPC pin
1
C9
AAN51_PQB7
3
A10
AAN52_PQA0
5
B10
AAN53_PQA1
7
A11
AAN54_PQA2
9
D10
AAN55_PQA3
11
C10
AAN56_PQA4
13
B11
AAN57_PQA5
15
D11
AAN58_PQA6
17
C11
AAN59_PQA7
27
D3
A_TPUCH0
29
A2
A_TPUCH1
30
E17
MPWM0
31
D4
A_TPUCH2
32
D18
MPWM1
33
C3
A_TPUCH3
35
A3
A_TPUCH4
36
D19
MPWM2
37
D5
A_TPUCH5
38
D20
MPWM3
39
B3
A_TPUCH6
42
F17
MPWM16
43
C4
A_TPUCH7
44
E18
MPWM17
45
A4
A_TPUCH8
47
C5
A_TPUCH9
48
F18
MPWM18
49
B4
A_TPUCH10
50
E19
MPWM19
51
B5
A_TPUCH11
53
A5
A_TPUCH12
54
A6
A_TPUCH15
55
C6
A_TPUCH13
56
C2
A_T2CLK
57
B6
A_TPUCH14
61
M2
/IRQ1B_SGP
62
M1
/IRQ0B_SGP
63
L3
/IRQ3B_SGP
64
M3
/IRQ2B_SGP
65
W18
/IRQ5B_SGP
66
L4
/IRQ4B_SGP
MOTOROLA
A-28
Signal name
See AAN48_PQB4
Analog input: passed on as a separate signal to the QADC.
See AAN52_PQA0
See AAN52_PQA0
See AAN52_PQA0
See AAN52_PQA0
See AAN52_PQA0
See AAN52_PQA0
See AAN52_PQA0
A_TPUCH0 - A_TPUCH15: Time Processor Unit A channel
See A_TPUCH0
MPWM0 - MPWM3, MPWM16 - MPWM19: Pulse width modulation
See A_TPUCH0
See MPWM0
See A_TPUCH0
See A_TPUCH0
See MPWM0
See A_TPUCH0
See MPWM0
See A_TPUCH0
See MPWM0
See A_TPUCH0
See MPWM0
See A_TPUCH0
See A_TPUCH0
See MPWM0
See A_TPUCH0
See MPWM0
See A_TPUCH0
See A_TPUCH0
See A_TPUCH0
See A_TPUCH0
to clock or gate the timer count register 2 (TCR2) within the TPU.
See A_TPUCH0
Interrupt request, SGPIO, reservation:
to indicate that the internal core initiated a transfer.
Interrupt request, SGPIO
Interrupt request, SGPIO, kill reservation,
retry: indicates to a master that the cycle is terminated
but should be repeated.
Interrupt request, SGPIO, cancel reservation: to clear its reservation.
Interrupt request, SGPIO, mode clock [1]:
sampled at the negation of /PORESET in order to
configure the PLL/clock mode.
Interrupt request, SGPIO, address type:
indicates one of the 16 "address types". The address type signals are
valid at the rising edge of the clock in which the special transfer start
(STS) is asserted.
Description corresponding to data sheet
EVB555
Quick Reference

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