The Ge/Pac 4020 Central Processor; Organization; Register And Control Flip-Flop Descriptions - GE PAC 4020 System Manual

THE GE/PAC 4020 CENTRAL PROCESSOR
ORGANIZATION
The GE/PAC
4020
computer is a binary, fixed
word length, single-address, highly parallel
computer utilizing a parallel adder for arithmetic
and word-logical functions and a serial adder for bit-
logical functio_ns. Figure 1 shows this processor's
internal organization in a simplified manner.
Of the three input-output methods shown, the
great majority of the work is done either by direct
memory access or by the arithmetic unit channels
via TIM/TOM. The channel to and from the "A"
register exists mainly to provide compatibility with
the GE/PAC
4040
computer and to drive the contact
sensing subsystem.
Certain functions - primarily indexing and the
secondary accumulator ("Q" location) - are per-
formed by a combination of dedicated core locations
and special control hardware, but are programmed
just as if they were active-component registers.
REGISTER AND CONTROL FLIP-FLOP DESCRIPTIONS
Not counting the registers and other hardware
used to implement its automatic program interrupt,
TIM/TOM input-output or optional Quadritect
memory protection features, the GE/PAC
4020
computer uses seven integrated circuit registers,
eight special-purpose dedicated core locations and
two full adders in executing programs:
A register
(24
bits, including sign). This is the
primary working register, involved in nearly all
instructions and tests. "A" uses the serial full adder
for bit operations and the parallel full adder for
arithmetic and word-logical operations. "A" con-
tains one of the two numbers involved in the ele-
mental arithmetic operations and receives all or the
most significant part of the result, except for
division, after which "A" contains the remainder and
"Q", the quotient.
Q location {24 bits, including sign). This
special-purpose core location, 10 8 in all systems,
supplemented by special hardware, acts as an ex-
tension of the "A" register during multiplication,
division, double-length logical and arithmetic shifts,
and double-length load, store, add and subtract
operations.
P register
(15
bits). This register contains the
address from which the next instruction will be
fetched.
It
works in conjunction with the parallel full
adder and the
"I''
register to implement the GE/PAC
computer's program control operations. The "P"
register can address 32, 768 core locations.
X locations (15 bits). These seven special-
purpose core locations, 1 - 7 8 in all systems, and
their associated hardware facilitate processing tables
of data by the method of automatic operand address
modification and addressing memory beyond 16K.
Five of the seven are available without restriction
and are stored by software whenever an interrupt is
acknowledged, along with "A", "Q", "P", and the
states of several important flip-flops. The other two
''X" locations are usable in special situations. The
unusually large number of index locations reduces
programming effort.
I register
(25
bits). This register contains the
instruction being executed and with the main adder
computes and holds the actual, direct operand
address (up to 32K) that results from the four
primary memory addressing modes and their
combinations.
J
register (five bits). This register contains the
lengths of shift instructions (0-3110 places) and the
count resulting from the bit-counting instructions.
The contents of
"J"
can be transferred into any of the
"X" locations by a single instruction, for further use.
B register
(24
bits). This register acts as a
buffer between the core registers, the arithmetic
unit, and various input-output channels.
It
also
assists in "Q" operations.
MAB
(memory address buff er,
15
bits). This
bufferconsists of selection circuits and addresses
both operands and instructions stored in up to 32K
locations.
MDR (memory data register,
25
bits including
parit~ This register holds operands and instruc-
tions on their way to and from core.
In addition to these registers, adders and core
locations, the GE/PAC
4020
computer employs four
control flip-flops. The states of these flip-flops are
stored in memory during interrupts or subroutine
entries by the save place and branch (SPB) instruc-
tion and are reloaded by load place and restore
(LPR).
Test flip-flop (TSTF). Numerous test instruc-
tions set or reset this flip-flop, which then controls
the direction of conditional branches. Separating
these functions allows very efficient testing and
branching in the numerous situations where there are
only two possible exits from a series of conditions
being tested.
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