Ge/Pac 4020 Computer Input-Output - GE PAC 4020 System Manual

A Table Input to Memory (TIM) or Table Output
from Memory (TOM) Control Word. To be described
later in this manual, this is the computer's main I/O
path to process subsystems and peripherals. It has
a buffering capacity of 189 eight-bit characters and
takes from the running program a total of 12. 7 or
30. 7 µs per word or character I/O operation, until
the table becomes full or empty. Then the TIM/TOM
hardware generates an "echo" interrupt, requiring
registers to be stored and a driver program to be
run to use the data or provide more.
Decrement Memory and Test (DMT). Described
in the "Special Commands and Features" section of
this manual, DMT provides a safe and efficient way
to count events, real-time and elapsed real-time,
and does not affect any of the programmable
registers.
The total time a GE/PAC 4020 computer will re-
quire to respond to a "permitted" interrupt consists
of the signal conditioning time constant required for
noise suppression, approximately 0.5 µs for the API
hardware itself to recognize an interrupt and gen-
erate an address for it, and the length of time until
the program encounters and executes a wired,
interruptible instruction.
Since program sequence or data might be lost
if
interrupts were permitted immediately after certain
instructions (such as branches, bit-counting instruc-
tions, instructions which load or test the index lo-
cations, and instructions which permit or inhibit the
API system itself), these instructions inhibit the API
system long enough for the one following instructions
to be executed, and are called "uninterruptible"
instructions for this reason.
The API system is available in increments of
eight levels from eight to 128 levels.
An optional mask register provides selective
inhibiting or enabling of groups of four sequential
levels. For a 128-level system, a 32-bit register is
provided. It is loaded from the lowest-order 16 bits
in the A register by load mask register commands
( LMR and LMR2).
To prevent the possibility of a continuous loop of
uninterruptible instructions effectively stalling the
central processor, and to be sure interrupts are
serviced in time, the computer optionally includes an
API watchdog timer. The first of the two timers
actually used to implement this function starts timing
whenever a non-inhibitable interrupt is requested.
If
a permit automatic interrupt (PAI) instruction is
not executed within one ms, program control is
forced to core location 248, the beginning of a reme-
dial program. The second timer performs a similar
function for all interrupts, non-inhibitable and
inhibitable, but uses a 30 ms period.
Implementing this useful option also requires the
Quadritect memory protection option.
Figure 4 shows a typical set of API level
assignments.
GE/PAC 4020 COMPUTER INPUT-OUTPUT
Direct Memory Access. The first of three types
of I/O provisions handles such high data-rate devices
as drum and disc bulk memories, other computers
or data acquisition systems, and GE high-speed
peripherals.
This I/O method operates in a true "cycle-
stealing" mode, requiring just one core cycle (1.6 µs)
to transfer a 24-bit word between the core and an ex-
ternal controller. The GE/PAC 4020 computer can
have up to three direct access channels and in the
case of high-speed peripherals, can drive more up to
eight controllers with one of the channels, permitting
a large number of very high-performance
peripherals.
TIM/TOM. TIM and TOM stand for Table Input
to Memory and Table Output from Memory. In this
mode, portions of the AU not used between instruc-
tions are employed by the special-purpose TIM/TOM
hardware to act as a controller between core mem-
ory, process I/O subsystems, and both low-speed
and moderate-speed peripherals. The result com-
bines economy and high speed; since no pro-
grammable registers are disturbed, it is not
necessary to store and reload them. While TIM/TOM
is somewhat slower than true cycle-stealing, it is
more than adequate for the service and far faster
than any other known I/O approach.
This feature also makes very efficient use of
memory as well as CPU time, since
it
can pack and
unpack one, two, three or four characters per 24-bit
word, depending on the code required by the device
or subsystem being driven. The table in memory
can be up to 63 words long. TIM/TOM is not an in-
struction, but a hardware function activated by an
interrupt. The interrupt response location holds a
TIM/TOM control word which is modified as the
operation proceeds. The control word contains a
starting address, word count, and character packing
instructions, as below:
23 18 17 16 15 14 13 0
N
p y
N =l's complement of the number of words to be
manipulated
C
=
P, initially, and is incremented as each
character is transferred
P = Packing Mode
00 = 4 char. /word (6 bits/char.)
01 = 3 char. /word (8 bits/char.)
10;;.. 2 char. /word (12 bits/char.)
11 = 1 char. /word (24 bits/ char. )
Y
= Starting Address minus 1
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